ERC: Check ElectricPower has voltage

examples/iterative_design_nand.py

@@ -132,6 +132,9 @@ def App():
     for ic_nand, xor_nand in zip(nand_ic.gates, nxor.nands):
         xor_nand.specialize(ic_nand)
 
+    # connect power to IC
+    nand_ic.power.connect(power_source.power)
+
     app.add(nand_ic)
 
     return app

examples/signal_processing.py

@@ -31,6 +31,12 @@ def __preinit__(self) -> None:
         # Specialize
         special = self.lowpass.specialize(F.FilterElectricalLC())
 
+        # set reference voltage
+        # TODO: this will be automatically set by the power supply
+        # once this example is more complete
+        special.in_.reference.voltage.merge(3 * P.V)
+        special.out.reference.voltage.merge(3 * P.V)
+
         # Construct
         special.get_trait(F.has_construction_dependency).construct()
 

src/faebryk/libs/app/erc.py

@@ -9,6 +9,7 @@
 from faebryk.core.graphinterface import Graph
 from faebryk.core.module import Module
 from faebryk.core.moduleinterface import ModuleInterface
+from faebryk.library.Operation import Operation
 from faebryk.libs.picker.picker import has_part_picked
 from faebryk.libs.util import groupby, print_stack
 
@@ -35,6 +36,11 @@ def __init__(self, faulting_ifs: Sequence[ModuleInterface], *args: object) -> No
         print(stack)
 
 
+class ERCFaultElectricPowerUndefinedVoltage(ERCFault):
+    def __init__(self, faulting_EP: F.ElectricPower, *args: object) -> None:
+        super().__init__([faulting_EP], *args)
+
+
 def simple_erc(G: Graph):
     """Simple ERC check.
 
@@ -54,12 +60,17 @@ def simple_erc(G: Graph):
     """
     logger.info("Checking graph for ERC violations")
 
-    # power short
+    # power short and power with undefined voltage
     electricpower = G.nodes_of_type(F.ElectricPower)
     logger.info(f"Checking {len(electricpower)} Power")
     for ep in electricpower:
         if ep.lv.is_connected_to(ep.hv):
             raise ERCFaultShort([ep], "shorted power")
+        if isinstance(ep.voltage.get_most_narrow(), (F.TBD, Operation)):
+            raise ERCFaultElectricPowerUndefinedVoltage(
+                ep,
+                f"ElectricPower with undefined or unsolved voltage: {ep.voltage}",
+            )
 
     # shorted nets
     nets = G.nodes_of_type(F.Net)

src/faebryk/libs/examples/buildutil.py

@@ -49,6 +49,9 @@ def apply_design_to_pcb(m: Module):
         m, recursive=True, loglvl=logging.DEBUG if DEV_MODE else logging.INFO
     )
 
+    G = m.get_graph()
+    run_checks(m, G)
+
     # TODO this can be prettier
     # picking ----------------------------------------------------------------
     modules = m.get_children_modules()
@@ -64,9 +67,6 @@ def apply_design_to_pcb(m: Module):
     pick_part_recursively(m)
     # -------------------------------------------------------------------------
 
-    G = m.get_graph()
-    run_checks(m, G)
-
     example_prj = Path(__file__).parent / Path("resources/example")
 
     if not DEV_MODE: