removed type from d_field; fix rt_field init order

examples/iterative_design_nand.py

@@ -37,7 +37,7 @@ class PowerSource(Module):
 
 
 class XOR_with_NANDS(F.LogicGates.XOR):
-    nands = L.node_list(4, lambda: F.LogicGates.NAND(F.Constant(2)))
+    nands = L.list_field(4, lambda: F.LogicGates.NAND(F.Constant(2)))
 
     def __init__(self):
         super().__init__(F.Constant(2))

examples/route.py

@@ -26,8 +26,8 @@
 
 
 class SubArray(Module):
-    unnamed = L.node_list(2, F.Electrical)
-    resistors = L.node_list(2, F.Resistor)
+    unnamed = L.list_field(2, F.Electrical)
+    resistors = L.list_field(2, F.Resistor)
 
     def __init__(self, extrude_y: float):
         super().__init__()
@@ -99,7 +99,7 @@ def pcb_routing_stategy_manual(self):
 
 
 class ResistorArray(Module):
-    unnamed = L.node_list(2, F.Electrical)
+    unnamed = L.list_field(2, F.Electrical)
 
     @L.rt_field
     def resistors(self):

new_holders_flat.py

@@ -69,7 +69,7 @@ def __preinit__(self):
 
 class LED2_WITHEXTRAT_IFS(LED2):
     extra: list[F.Electrical] = field(default_factory=lambda: times(2, F.Electrical))
-    extra2: list[F.Electrical] = L.node_list(2, F.Electrical)
+    extra2: list[F.Electrical] = L.list_field(2, F.Electrical)
 
     @L.rt_field
     def bridge(self):

src/faebryk/core/node.py

@@ -5,6 +5,7 @@
 from typing import TYPE_CHECKING, Any, Callable, Iterable, Type, get_args, get_origin
 
 from deprecated import deprecated
+from more_itertools import partition
 
 from faebryk.core.core import ID_REPR, FaebrykLibObject
 from faebryk.core.graphinterface import (
@@ -21,7 +22,6 @@
     times,
     try_avoid_endless_recursion,
 )
-from more_itertools import partition
 
 if TYPE_CHECKING:
     from faebryk.core.trait import Trait, TraitImpl
@@ -41,10 +41,8 @@ class FieldContainerError(FieldError):
     pass
 
 
-def node_list[T: Node](n: int, if_type: type[T]) -> list[T]:
-    out = d_field(lambda: times(n, if_type))
-    out.type = if_type
-    return out
+def list_field[T: Node](n: int, if_type: Callable[[], T]) -> list[T]:
+    return d_field(lambda: times(n, if_type))
 
 
 class fab_field:
@@ -71,11 +69,10 @@ def __get__(self, instance: T, owner: type | None = None) -> Any:
 
 class _d_field[T](fab_field):
     def __init__(self, default_factory: Callable[[], T]) -> None:
-        self.type = None
         self.default_factory = default_factory
 
     def __repr__(self) -> str:
-        return f"{super().__repr__()}({self.type=}, {self.default_factory=})"
+        return f"{super().__repr__()}{self.default_factory=})"
 
 
 def d_field[T](default_factory: Callable[[], T]) -> T:
@@ -89,9 +86,7 @@ def _(*args: P.args, **kwargs: P.kwargs) -> Callable[[], T]:
         def __() -> T:
             return con(*args, **kwargs)
 
-        out = _d_field(__)
-        out.type = con
-        return out
+        return _d_field(__)
 
     return _
 
@@ -120,6 +115,9 @@ def __init__(self, node: "Node", other: "Node", *args: object) -> None:
         )
 
 
+class NodeNoParent(NodeException): ...
+
+
 class Node(FaebrykLibObject, metaclass=PostInitCaller):
     runtime_anon: list["Node"]
     runtime: dict[str, "Node"]
@@ -203,9 +201,6 @@ def all_anno(cls):
 
         annos = all_anno(cls)
         vars_ = all_vars(cls)
-        for name, obj in vars_.items():
-            if isinstance(obj, _d_field) and obj.type is None:
-                obj.type = annos[name]
 
         def is_node_field(obj):
             def is_genalias_node(obj):
@@ -229,12 +224,7 @@ def is_genalias_node(obj):
                 return issubclass(obj, LL_Types)
 
             if isinstance(obj, _d_field):
-                t = obj.type
-                if isinstance(t, type):
-                    return issubclass(t, LL_Types)
-
-                if get_origin(t):
-                    return is_genalias_node(t)
+                return True
 
             if get_origin(obj):
                 return is_genalias_node(obj)
@@ -267,9 +257,12 @@ def is_genalias_node(obj):
         # "| {type(obj)}"
         #    )
 
+        added_objects: dict[str, Node | GraphInterface] = {}
         objects: dict[str, Node | GraphInterface] = {}
 
         def handle_add(name, obj):
+            del objects[name]
+            added_objects[name] = obj
             if isinstance(obj, GraphInterface):
                 self._handle_add_gif(name, obj)
             elif isinstance(obj, Node):
@@ -307,22 +300,8 @@ def setup_gen_alias(name, obj):
                 return
 
             if isinstance(obj, _d_field):
-                t = obj.type
-
-                if isinstance(obj, _d_field):
-                    inst = append(name, obj.default_factory())
-                    setattr(self, name, inst)
-                    return
-
-                if isinstance(t, type):
-                    setattr(self, name, append(name, t()))
-                    return
-
-                if get_origin(t):
-                    setup_gen_alias(name, t)
-                    return
-
-                raise NotImplementedError()
+                setattr(self, name, append(name, obj.default_factory()))
+                return
 
             if isinstance(obj, type):
                 setattr(self, name, append(name, obj()))
@@ -338,19 +317,17 @@ def setup_gen_alias(name, obj):
         for name, obj in nonrt:
             setup_field(name, obj)
 
-        for name, obj in objects.items():
+        for name, obj in list(objects.items()):
             handle_add(name, obj)
-        obj_old = dict(objects)
 
         # rt fields depend on full self
         for name, obj in rt:
             setup_field(name, obj)
 
-        for name, obj in objects.items():
-            if name not in obj_old:
+            for name, obj in list(objects.items()):
                 handle_add(name, obj)
 
-        return objects, clsfields
+        return added_objects, clsfields
 
     def __new__(cls, *args, **kwargs):
         out = super().__new__(cls)
@@ -424,7 +401,7 @@ def get_parent(self):
     def get_name(self):
         p = self.get_parent()
         if not p:
-            raise Exception("Parent required for name")
+            raise NodeNoParent(self, "Parent required for name")
         return p[1]
 
     def get_hierarchy(self) -> list[tuple["Node", str]]:

src/faebryk/exporters/pcb/kicad/transformer.py

@@ -516,7 +516,7 @@ def mark(node: R) -> R:
     def insert(self, obj: Any):
         self._insert(obj)
 
-    def _get_pcb_node_list(self, node: R, prefix: str = "") -> list[R]:
+    def _get_pcb_list_field(self, node: R, prefix: str = "") -> list[R]:
         root = self.pcb
         key = prefix + type(node).__name__.removeprefix("C_") + "s"
 
@@ -529,10 +529,10 @@ def _get_pcb_node_list(self, node: R, prefix: str = "") -> list[R]:
 
     def _insert(self, obj: Any, prefix: str = ""):
         obj = PCB_Transformer.mark(obj)
-        self._get_pcb_node_list(obj, prefix=prefix).append(obj)
+        self._get_pcb_list_field(obj, prefix=prefix).append(obj)
 
     def _delete(self, obj: Any, prefix: str = ""):
-        self._get_pcb_node_list(obj, prefix=prefix).remove(obj)
+        self._get_pcb_list_field(obj, prefix=prefix).remove(obj)
 
     def insert_via(
         self, coord: tuple[float, float], net: str, size_drill: tuple[float, float]

src/faebryk/library/B4B_ZR_SM4_TF.py

@@ -7,8 +7,8 @@
 
 
 class B4B_ZR_SM4_TF(Module):
-    pin = L.node_list(4, F.Electrical)
-    mount = L.node_list(2, F.Electrical)
+    pin = L.list_field(4, F.Electrical)
+    mount = L.list_field(2, F.Electrical)
 
     datasheet = L.f_field(F.has_datasheet_defined)(
         "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2304140030_BOOMELE-Boom-Precision-Elec-1-5-4P_C145997.pdf"

src/faebryk/library/Button.py

@@ -11,7 +11,7 @@
 
 
 class Button(Module):
-    unnamed = L.node_list(2, F.Electrical)
+    unnamed = L.list_field(2, F.Electrical)
 
     designator_prefix = L.f_field(F.has_designator_prefix_defined)("S")
 

src/faebryk/library/CBM9002A_56ILG.py

@@ -16,17 +16,17 @@ class CBM9002A_56ILG(Module):
     # ----------------------------------------
     #     modules, interfaces, parameters
     # ----------------------------------------
-    PA = L.node_list(8, F.ElectricLogic)
-    PB = L.node_list(8, F.ElectricLogic)
-    PD = L.node_list(8, F.ElectricLogic)
+    PA = L.list_field(8, F.ElectricLogic)
+    PB = L.list_field(8, F.ElectricLogic)
+    PD = L.list_field(8, F.ElectricLogic)
     usb: F.USB2_0
     i2c: F.I2C
 
     avcc: F.ElectricPower
     vcc: F.ElectricPower
 
-    rdy = L.node_list(2, F.ElectricLogic)
-    ctl = L.node_list(3, F.ElectricLogic)
+    rdy = L.list_field(2, F.ElectricLogic)
+    ctl = L.list_field(3, F.ElectricLogic)
     reset: F.ElectricLogic
     wakeup: F.ElectricLogic
 

src/faebryk/library/CBM9002A_56ILG_Reference_Design.py

@@ -20,17 +20,17 @@ class CBM9002A_56ILG_Reference_Design(Module):
     reset_lowpass_cap: F.Capacitor
     oscillator: F.Crystal_Oscillator
 
-    PA = L.node_list(8, F.ElectricLogic)
-    PB = L.node_list(8, F.ElectricLogic)
-    PD = L.node_list(8, F.ElectricLogic)
+    PA = L.list_field(8, F.ElectricLogic)
+    PB = L.list_field(8, F.ElectricLogic)
+    PD = L.list_field(8, F.ElectricLogic)
     usb: F.USB2_0
     i2c: F.I2C
 
     avcc: F.ElectricPower
     vcc: F.ElectricPower
 
-    rdy = L.node_list(2, F.ElectricLogic)
-    ctl = L.node_list(3, F.ElectricLogic)
+    rdy = L.list_field(2, F.ElectricLogic)
+    ctl = L.list_field(3, F.ElectricLogic)
     reset: F.ElectricLogic
     wakeup: F.ElectricLogic
 

src/faebryk/library/Capacitor.py

@@ -23,7 +23,7 @@ class TemperatureCoefficient(IntEnum):
         X8R = auto()
         C0G = auto()
 
-    unnamed = L.node_list(2, F.Electrical)
+    unnamed = L.list_field(2, F.Electrical)
 
     capacitance: F.TBD[Quantity]
     rated_voltage: F.TBD[Quantity]

src/faebryk/library/Common_Mode_Filter.py

@@ -11,7 +11,7 @@
 
 
 class Common_Mode_Filter(Module):
-    c_a = L.node_list(2, F.Electrical)
-    c_b = L.node_list(2, F.Electrical)
+    c_a = L.list_field(2, F.Electrical)
+    c_b = L.list_field(2, F.Electrical)
 
     designator_prefix = L.f_field(F.has_designator_prefix_defined)("FL")

src/faebryk/library/Crystal.py

@@ -21,7 +21,7 @@ class Crystal(Module):
     load_impedance: F.TBD[Quantity]
 
     gnd: F.Electrical
-    unnamed = L.node_list(2, F.Electrical)
+    unnamed = L.list_field(2, F.Electrical)
 
     # ----------------------------------------
     #               parameters

src/faebryk/library/Crystal_Oscillator.py

@@ -15,7 +15,7 @@ class Crystal_Oscillator(Module):
     #     modules, interfaces, parameters
     # ----------------------------------------
     crystal: F.Crystal
-    capacitors = L.node_list(2, F.Capacitor)
+    capacitors = L.list_field(2, F.Capacitor)
 
     power: F.ElectricPower
     p: F.Electrical

src/faebryk/library/DIP.py

@@ -31,7 +31,7 @@ def get_kicad_footprint() -> str:
                     longpads="_LongPads" if self.long_pads else "",
                 )
 
-        return _has_kicad_footprint
+        return _has_kicad_footprint()
 
     equal_pins_in_ifs: F.has_equal_pins_in_ifs
     attach_via_pinmap: F.can_attach_via_pinmap_equal

src/faebryk/library/EEPROM.py

@@ -30,7 +30,7 @@ def set_address(self, addr: int):
     power: F.ElectricPower
     i2c: F.I2C
     write_protect: F.ElectricLogic
-    address = L.node_list(3, F.ElectricLogic)
+    address = L.list_field(3, F.ElectricLogic)
 
     # ----------------------------------------
     #                traits

src/faebryk/library/ESP32.py

@@ -27,15 +27,15 @@ def CHANNELS(self):
 
 
 class _ESP_SDIO(ModuleInterface):
-    DATA = L.node_list(4, F.Electrical)
+    DATA = L.list_field(4, F.Electrical)
     CLK: F.Electrical
     CMD: F.Electrical
     GND: F.Electrical
 
 
 class _ESP32_EMAC(ModuleInterface):
-    TXD = L.node_list(4, F.Electrical)
-    RXD = L.node_list(4, F.Electrical)
+    TXD = L.list_field(4, F.Electrical)
+    RXD = L.list_field(4, F.Electrical)
     TX_CLK: F.Electrical
     RX_CLK: F.Electrical
     TX_EN: F.Electrical
@@ -123,22 +123,22 @@ class ESP32(Module):
     GND: F.Electrical
 
     # High Level Functions
-    F.I2C = L.node_list(2, F.I2C)
+    F.I2C = L.list_field(2, F.I2C)
     SDIO_SLAVE: _ESP_SDIO
-    SDIO_HOST = L.node_list(2, _ESP_SDIO)
+    SDIO_HOST = L.list_field(2, _ESP_SDIO)
     UART: F.UART_Base
     JTAG: F.JTAG
-    TOUCH = L.node_list(10, F.Electrical)
-    GPIO = L.node_list(40 - 6, F.Electrical)
-    RTC_GPIO = L.node_list(18, F.Electrical)
+    TOUCH = L.list_field(10, F.Electrical)
+    GPIO = L.list_field(40 - 6, F.Electrical)
+    RTC_GPIO = L.list_field(18, F.Electrical)
     ADC = L.d_field(
         lambda: (
             None,
             _ESP_ADC(channel_count=8),
             _ESP_ADC(channel_count=10),
         )
     )
-    SPI = L.node_list(4, _ESP32_SPI)
+    SPI = L.list_field(4, _ESP32_SPI)
     EMAC: _ESP32_EMAC
 
     # Power

src/faebryk/library/ESP32_C3.py

@@ -23,11 +23,11 @@ class ESP32_C3(Module):
     enable: F.ElectricLogic
     xtal_p: F.Electrical
     xtal_n: F.Electrical
-    gpio = L.node_list(22, F.ElectricLogic)
+    gpio = L.list_field(22, F.ElectricLogic)
     # TODO: map peripherals to GPIOs with pinmux
     usb: F.USB2_0
     i2c: F.I2C
-    uart = L.node_list(2, F.UART_Base)
+    uart = L.list_field(2, F.UART_Base)
     # ... etc
 
     designator_prefix = L.f_field(F.has_designator_prefix_defined)("U")