Fix layout in RPPicoBase ref design

atopile · Oct 18, 2024 · cc29b3b · cc29b3b
1 parent 19d0d4b
commit cc29b3b
Showing 1 changed file with 34 additions and 6 deletions.
diff --git a/src/faebryk/library/RaspberryPiPicoBase_ReferenceDesign.py b/src/faebryk/library/RaspberryPiPicoBase_ReferenceDesign.py
@@ -289,8 +289,11 @@ def pcb_layout(self):
                                 ),
                                 LVL(
                                     mod_type=F.Resistor,
-                                    layout=LayoutAbsolute(
-                                        Point((0, 2.5, 0, L.NONE)),
+                                    layout=LayoutExtrude(
+                                        base=Point((-7, -1.5, 0, L.NONE)),
+                                        vector=(0, 2.25, 180),
+                                        reverse_order=True,
+                                        dynamic_rotation=True,
                                     ),
                                 ),
                             ],
@@ -339,10 +342,35 @@ def pcb_layout(self):
                         ),
                     ),
                     LVL(
-                        mod_type=F.Resistor,
-                        layout=LayoutExtrude(
-                            base=Point((0.75, -6, 0, L.NONE)),
-                            vector=(1.25, 0, 270),
+                        mod_type=self.PICO_ADC_VoltageReference,
+                        layout=LayoutAbsolute(
+                            Point((0.75, -6, 0, L.NONE)),
+                        ),
+                        children_layout=LayoutTypeHierarchy(
+                            layouts=[
+                                LVL(
+                                    mod_type=F.FilterElectricalRC,
+                                    layout=LayoutAbsolute(
+                                        Point((0, 0, 0, L.NONE)),
+                                    ),
+                                    children_layout=LayoutTypeHierarchy(
+                                        layouts=[
+                                            LVL(
+                                                mod_type=F.Capacitor,
+                                                layout=LayoutAbsolute(
+                                                    Point((0, 0, 0, L.NONE)),
+                                                ),
+                                            ),
+                                            LVL(
+                                                mod_type=F.Resistor,
+                                                layout=LayoutAbsolute(
+                                                    Point((1.25, 0, 270, L.NONE)),
+                                                ),
+                                            ),
+                                        ],
+                                    ),
+                                ),
+                            ],
                         ),
                     ),
                 ]