Library: Additions, changes and fixes (#89)

* Add missing traits

* Various fixes and name changes

* Change UART to include UART_Base

* Add SM712_ES

* Add W25Q16JVUXIQ

* Add Pico base design

* Fix unused imports

* Fix _F

* Add BNC con and USB ESD protection chip

* Use LayoutNextTo for crystal osc

* Clean up USB2 ESD protection base

* Clean up Header

* Clean up CH344Q ref design

* Add missing decoupling caps for LDO in USB2514 ref design

* Fix layout in RPPicoBase ref design

* Fix layout

src/faebryk/library/CH344Q_ReferenceDesign.py

@@ -59,17 +59,17 @@ def pcb_layout(self):
                     ),
                     LVL(
                         mod_type=F.LDO,
-                        layout=LayoutAbsolute(Point((7.5, 0, 0, L.NONE))),
+                        layout=LayoutAbsolute(Point((9.5, 0, 0, L.NONE))),
                     ),
                     LVL(
                         mod_type=F.LEDIndicator,
                         layout=LayoutExtrude(
-                            base=Point((-2.5, -11, 180, L.NONE)), vector=(0, 1.75, 0)
+                            base=Point((-5.75, 7.5, 0, L.NONE)), vector=(-1.75, 0, 90)
                         ),
                     ),
                     LVL(
                         mod_type=F.PoweredLED,
-                        layout=LayoutAbsolute(Point((-2.5, -16.25, 0, L.NONE))),
+                        layout=LayoutAbsolute(Point((5, -8, 90, L.NONE))),
                     ),
                     LVL(
                         mod_type=F.FilterElectricalRC,
@@ -87,22 +87,17 @@ def __preinit__(self):
         # ------------------------------------
         #           connections
         # ------------------------------------
-        self.usb_uart_converter.power.decoupled.decouple().capacitance.merge(
-            F.Range.from_center_rel(1 * P.uF, 0.05)
-        )  # TODO: per pin
+        self.usb_uart_converter.power.decoupled.decouple().specialize(
+            F.MultiCapacitor(4)
+        ).set_equal_capacitance_each(F.Range.from_center_rel(100 * P.nF, 0.05))
         self.vbus_fused.connect_via(self.ldo, pwr_3v3)
 
         self.usb.usb_if.d.connect(self.usb_uart_converter.usb)
 
         self.usb_uart_converter.act.connect(self.led_act.logic_in)
         self.usb_uart_converter.indicator_rx.connect(self.led_rx.logic_in)
         self.usb_uart_converter.indicator_tx.connect(self.led_tx.logic_in)
-        pwr_3v3.connect(
-            self.power_led.power,
-            self.led_rx.power_in,
-            self.led_tx.power_in,
-            self.led_act.power_in,
-        )
+        pwr_3v3.connect(self.power_led.power)
 
         self.usb_uart_converter.osc[1].connect(self.oscillator.xtal_if.xin)
         self.usb_uart_converter.osc[0].connect(self.oscillator.xtal_if.xout)
@@ -125,6 +120,16 @@ def __preinit__(self):
         self.oscillator.crystal.load_capacitance.merge(
             F.Range.from_center(8 * P.pF, 10 * P.pF)
         )  # TODO: should be property of crystal when picked
+        self.oscillator.current_limiting_resistor.resistance.merge(
+            F.Constant(0 * P.ohm)
+        )
+
+        self.ldo.power_in.decoupled.decouple().capacitance.merge(
+            F.Range.from_center_rel(100 * P.nF, 0.1)
+        )
+        self.ldo.power_out.decoupled.decouple().capacitance.merge(
+            F.Range.from_center_rel(100 * P.nF, 0.1)
+        )
 
         self.usb.usb_if.buspower.max_current.merge(
             F.Range.from_center_rel(500 * P.mA, 0.1)

src/faebryk/library/Crystal_Oscillator.py

@@ -36,6 +36,8 @@ def __preinit__(self):
         for cap in self.capacitors:
             cap.capacitance.merge(self.capacitance)
 
+        self.current_limiting_resistor.allow_removal_if_zero()
+
         # ----------------------------------------
         #                traits
         # ----------------------------------------
@@ -59,12 +61,34 @@ def __preinit__(self):
     @L.rt_field
     def pcb_layout(self):
         from faebryk.exporters.pcb.layout.absolute import LayoutAbsolute
-        from faebryk.exporters.pcb.layout.extrude import LayoutExtrude
+        from faebryk.exporters.pcb.layout.heuristic_decoupling import Params
+        from faebryk.exporters.pcb.layout.next_to import LayoutNextTo
         from faebryk.exporters.pcb.layout.typehierarchy import LayoutTypeHierarchy
 
         Point = F.has_pcb_position.Point
         L = F.has_pcb_position.layer_type
 
+        self.capacitors[0].add_trait(
+            F.has_pcb_layout_defined(
+                layout=LayoutNextTo(
+                    target=self.crystal.unnamed[0],
+                    params=Params(
+                        distance_between_pad_edges=1.25, extra_rotation_of_footprint=90
+                    ),
+                )
+            )
+        )
+        self.capacitors[1].add_trait(
+            F.has_pcb_layout_defined(
+                layout=LayoutNextTo(
+                    target=self.crystal.unnamed[1],
+                    params=Params(
+                        distance_between_pad_edges=1.25, extra_rotation_of_footprint=90
+                    ),
+                )
+            )
+        )
+
         return F.has_pcb_layout_defined(
             LayoutTypeHierarchy(
                 layouts=[
@@ -74,14 +98,14 @@ def pcb_layout(self):
                             Point((0, 0, 0, L.NONE)),
                         ),
                     ),
-                    LayoutTypeHierarchy.Level(
-                        mod_type=F.Capacitor,
-                        layout=LayoutExtrude(
-                            base=Point((-3, 0, 0, L.NONE)),
-                            vector=(0, 6, 180),
-                            dynamic_rotation=True,
-                        ),
-                    ),
+                    # LayoutTypeHierarchy.Level(
+                    #    mod_type=F.Capacitor,
+                    #    layout=LayoutExtrude(
+                    #        base=Point((-3, 0, 0, L.NONE)),
+                    #        vector=(0, 6, 180),
+                    #        dynamic_rotation=True,
+                    #    ),
+                    # ),
                     LayoutTypeHierarchy.Level(
                         mod_type=F.Resistor,
                         layout=LayoutAbsolute(Point((-3, -3, 0, L.NONE))),

src/faebryk/library/ElecSuper_PSM712_ES.py

@@ -0,0 +1,64 @@
+# This file is part of the faebryk project
+# SPDX-License-Identifier: MIT
+
+import logging
+
+import faebryk.library._F as F  # noqa: F401
+from faebryk.core.module import Module
+from faebryk.libs.library import L  # noqa: F401
+from faebryk.libs.picker.picker import DescriptiveProperties
+from faebryk.libs.units import P  # noqa: F401
+
+logger = logging.getLogger(__name__)
+
+
+class ElecSuper_PSM712_ES(Module):
+    """
+    RS485 bus ESD and surge protection
+
+    17A 350W Bidirectional SOT-23
+    ESD and Surge Protection (TVS/ESD) ROHS
+    """
+
+    # ----------------------------------------
+    #     modules, interfaces, parameters
+    # ----------------------------------------
+    rs485: F.RS485
+
+    # ----------------------------------------
+    #                 traits
+    # ----------------------------------------
+    designator_prefix = L.f_field(F.has_designator_prefix_defined)(
+        F.has_designator_prefix.Prefix.U
+    )
+    descriptive_properties = L.f_field(F.has_descriptive_properties_defined)(
+        {
+            DescriptiveProperties.manufacturer: "ElecSuper",
+            DescriptiveProperties.partno: "PSM712-ES",
+        }
+    )
+    datasheet = L.f_field(F.has_datasheet_defined)(
+        "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2209191800_ElecSuper-PSM712-ES_C5180294.pdf"
+    )
+
+    @L.rt_field
+    def pin_association_heuristic(self):
+        return F.has_pin_association_heuristic_lookup_table(
+            mapping={
+                self.rs485.diff_pair.n.signal: ["1"],
+                self.rs485.diff_pair.p.signal: ["2"],
+                self.rs485.diff_pair.n.reference.lv: ["3"],
+            },
+            accept_prefix=False,
+            case_sensitive=False,
+        )
+
+    def __preinit__(self):
+        # ------------------------------------
+        #           connections
+        # ------------------------------------
+
+        # ------------------------------------
+        #          parametrization
+        # ------------------------------------
+        pass

src/faebryk/library/Header.py

@@ -21,8 +21,7 @@ class PadType(Enum):
 
     class Angle(Enum):
         STRAIGHT = auto()
-        VERTICAL90 = auto()
-        HORIZONTAL90 = auto()
+        ANGLE_90 = auto()
 
     def __init__(
         self,
@@ -38,6 +37,9 @@ def __preinit__(self):
         self.pin_count_vertical.merge(self._vertical_pin_count)
 
     pin_pitch: F.TBD[Quantity]
+    mating_pin_lenght: F.TBD[Quantity]
+    conection_pin_lenght: F.TBD[Quantity]
+    spacer_height: F.TBD[Quantity]
     pin_type: F.TBD[PinType]
     pad_type: F.TBD[PadType]
     angle: F.TBD[Angle]
@@ -46,11 +48,17 @@ def __preinit__(self):
     pin_count_vertical: F.TBD[int]
 
     @L.rt_field
-    def unnamed(self):
+    def contact(self):
         return times(
             self._horizontal_pin_count * self._vertical_pin_count, F.Electrical
         )
 
     designator_prefix = L.f_field(F.has_designator_prefix_defined)(
         F.has_designator_prefix.Prefix.J
     )
+
+    @L.rt_field
+    def can_attach_to_footprint(self):
+        return F.can_attach_to_footprint_via_pinmap(
+            pinmap={f"{i+1}": self.contact[i] for i in range(len(self.contact))}
+        )

src/faebryk/library/INA228_ReferenceDesign.py

@@ -36,13 +36,13 @@ def __preinit__(self):
             self.power_in.voltage.merge(
                 self.power_out.voltage
             )  # TODO: minus voltagedrop over shunt
-            self.shunt_sense.p.connect_via(self.shunt, self.shunt_sense.n)
+            self.shunt_sense.p.signal.connect_via(self.shunt, self.shunt_sense.n.signal)
             if self._lowside:
+                self.power_in.lv.connect_via(self.shunt, self.power_out.lv)
+                self.power_in.hv.connect(self.power_out.hv)
+            else:
                 self.power_in.hv.connect_via(self.shunt, self.power_out.hv)
                 self.power_in.lv.connect(self.power_out.lv)
-            else:
-                # TODO:short? self.power_in.lv.connect_via(self.shunt, self.power_out.lv
-                self.power_in.hv.connect(self.power_out.hv)
 
             if self._filtered:
                 raise NotImplementedError

src/faebryk/library/LDO.py

@@ -54,6 +54,10 @@ def single_electric_reference(self):
             F.ElectricLogic.connect_all_module_references(self, gnd_only=True)
         )
 
+    @L.rt_field
+    def decoupled(self):
+        return F.can_be_decoupled_rails(self.power_in, self.power_out)
+
     @L.rt_field
     def can_bridge(self):
         return F.can_bridge_defined(self.power_in, self.power_out)

src/faebryk/library/MultiSPI.py

@@ -12,8 +12,8 @@ def __init__(self, data_lane_count: int) -> None:
         super().__init__()
         self._data_lane_count = data_lane_count
 
-    clk: F.ElectricLogic
-    cs: F.ElectricLogic
+    clock: F.ElectricLogic
+    chip_select: F.ElectricLogic
 
     @L.rt_field
     def data(self):

src/faebryk/library/Powered_Relay.py

@@ -30,14 +30,9 @@ def __preinit__(self):
 
         self.relay_driver.power_in.connect(self.power)
         self.relay_driver.logic_in.connect(self.enable)
-        self.relay_driver.switched_power_out.lv.connect(self.relay.coil_n)
-        self.relay_driver.switched_power_out.hv.connect(self.relay.coil_p)
+        self.relay_driver.switched_power_out.connect(self.relay.coil_power)
 
-        self.relay.coil_n.connect_via(self.flyback_diode, self.relay.coil_p)
-        self.indicator.power.connect(self.relay_driver.switched_power_out)
-
-    @L.rt_field
-    def single_electric_reference(self):
-        return F.has_single_electric_reference_defined(
-            F.ElectricLogic.connect_all_module_references(self, gnd_only=True)
+        self.relay.coil_power.lv.connect_via(
+            self.flyback_diode, self.relay.coil_power.hv
         )
+        self.indicator.power.connect(self.relay_driver.switched_power_out)

src/faebryk/library/RP2040.py

@@ -53,7 +53,8 @@ def bridge(self):
     class SPI(F.SPI):
         cs: F.ElectricLogic
 
-    class UART(F.UART_Base):
+    class UART(ModuleInterface):
+        base_uart: F.UART_Base
         rts: F.ElectricLogic
         cts: F.ElectricLogic
 
@@ -126,11 +127,11 @@ def __preinit__(self):
 
         # QSPI pins reusable for soft gpio
         self.qspi.data[3].signal.connect(self.io_soft[0])
-        self.qspi.clk.signal.connect(self.io_soft[1])
+        self.qspi.clock.signal.connect(self.io_soft[1])
         self.qspi.data[0].signal.connect(self.io_soft[2])
         self.qspi.data[2].signal.connect(self.io_soft[3])
         self.qspi.data[1].signal.connect(self.io_soft[4])
-        self.qspi.cs.signal.connect(self.io_soft[5])
+        self.qspi.chip_select.signal.connect(self.io_soft[5])
 
         # ADC pins shared with GPIO
         self.adc[0].signal.connect(self.io[26])
@@ -210,17 +211,17 @@ def attach_to_footprint(self):
                 "43": self.power_adc.hv,
                 "44": self.core_regulator.power_in.hv,
                 "45": self.core_regulator.power_out.hv,
-                "46": self.usb.n,
-                "47": self.usb.p,
+                "46": self.usb.n.signal,
+                "47": self.usb.p.signal,
                 "48": self.power_usb_phy.hv,
                 "49": self.power_io.hv,
                 "50": self.power_core.hv,
                 "51": self.qspi.data[3].signal,
-                "52": self.qspi.clk.signal,
+                "52": self.qspi.clock.signal,
                 "53": self.qspi.data[0].signal,
                 "54": self.qspi.data[2].signal,
                 "55": self.qspi.data[1].signal,
-                "56": self.qspi.cs.signal,
+                "56": self.qspi.chip_select.signal,
                 "57": self.power_io.lv,  # center pad
             }
         )
@@ -263,18 +264,18 @@ def pin_association_heuristic(self):
                 self.io[8]: ["GPIO8"],
                 self.io[9]: ["GPIO9"],
                 self.power_io.hv: ["IOVDD"],
-                self.qspi.clk.signal: ["QSPI_SCLK"],
+                self.qspi.clock.signal: ["QSPI_SCLK"],
                 self.qspi.data[0].signal: ["QSPI_SD0"],
                 self.qspi.data[1].signal: ["QSPI_SD1"],
                 self.qspi.data[2].signal: ["QSPI_SD2"],
                 self.qspi.data[3].signal: ["QSPI_SD3"],
-                self.qspi.cs.signal: ["QSPI_SS"],
+                self.qspi.chip_select.signal: ["QSPI_SS", "QSPI_SS_N"],
                 self.run.signal: ["RUN"],
                 self.swd.clk.signal: ["SWCLK"],
                 self.swd.dio.signal: ["SWD"],
                 self.factory_test_enable: ["TESTEN"],
-                self.usb.n: ["USB_DM"],
-                self.usb.p: ["USB_DP"],
+                self.usb.n.signal: ["USB_DM"],
+                self.usb.p.signal: ["USB_DP"],
                 self.power_usb_phy.hv: ["USB_VDD"],
                 self.core_regulator.power_in.hv: ["VREG_IN"],
                 self.core_regulator.power_out.hv: ["VREG_VOUT"],