Add: missing module interfaces

atopile · Sep 5, 2024 · c95a8ee · c95a8ee
1 parent f67a6e5
commit c95a8ee
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diff --git a/src/faebryk/library/RS232.py b/src/faebryk/library/RS232.py
@@ -9,6 +9,12 @@
 class RS232(ModuleInterface):
     tx: F.ElectricLogic
     rx: F.ElectricLogic
+    dtr: F.ElectricLogic
+    dcd: F.ElectricLogic
+    dsr: F.ElectricLogic
+    ri: F.ElectricLogic
+    rts: F.ElectricLogic
+    cts: F.ElectricLogic
 
     @L.rt_field
     def single_electric_reference(self):

diff --git a/src/faebryk/library/UART.py b/src/faebryk/library/UART.py
@@ -11,3 +11,5 @@ class UART(ModuleInterface):
     cts: F.ElectricLogic
     dtr: F.ElectricLogic
     dsr: F.ElectricLogic
+    dcd: F.ElectricLogic
+    ri: F.ElectricLogic