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Add: * Analog_Devices_ADM2587EBRWZ * PANASONIC_AQY212EHAX * RaspberryPiPico * SK6812 * Fix logic reference connection * Add RP Pico design * Fix pin connection * Fix switch and traits * Fix some layouts
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,127 @@ | ||
| # This file is part of the faebryk project | ||
| # SPDX-License-Identifier: MIT | ||
|
|
||
| import logging | ||
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| import faebryk.library._F as F # noqa: F401 | ||
| from faebryk.core.module import Module | ||
| from faebryk.libs.library import L # noqa: F401 | ||
| from faebryk.libs.picker.picker import DescriptiveProperties | ||
| from faebryk.libs.units import P | ||
| from faebryk.libs.util import assert_once # noqa: F401 | ||
|
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| logger = logging.getLogger(__name__) | ||
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| class Analog_Devices_ADM2587EBRWZ(Module): | ||
| """ | ||
| Signal and power isolated RS-485 full/half-duplex transceiver with | ||
| ±15 kV ESD protection | ||
| """ | ||
|
|
||
| # ---------------------------------------- | ||
| # modules, interfaces, parameters | ||
| # ---------------------------------------- | ||
| power_unisolated: F.ElectricPower | ||
| power_isolated_out: F.ElectricPower | ||
| power_isolated_in: F.ElectricPower | ||
| uart: F.UART_Base | ||
| read_enable: F.ElectricLogic | ||
| write_enable: F.ElectricLogic | ||
| rs485: F.RS485HalfDuplex | ||
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| # ---------------------------------------- | ||
| # traits | ||
| # ---------------------------------------- | ||
| lcsc_id = L.f_field(F.has_descriptive_properties_defined)({"LCSC": "C12081"}) | ||
| designator_prefix = L.f_field(F.has_designator_prefix_defined)( | ||
| F.has_designator_prefix.Prefix.U | ||
| ) | ||
| descriptive_properties = L.f_field(F.has_descriptive_properties_defined)( | ||
| { | ||
| DescriptiveProperties.manufacturer: "Analog Devices", | ||
| DescriptiveProperties.partno: "ADM2587EBRWZ-REEL7", | ||
| } | ||
| ) | ||
| datasheet = L.f_field(F.has_datasheet_defined)( | ||
| "https://www.lcsc.com/datasheet/lcsc_datasheet_1809121646_Analog-Devices-ADM2587EBRWZ-REEL7_C12081.pdf" # noqa: E501 | ||
| ) | ||
|
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||
| @L.rt_field | ||
| def can_attach_to_footprint(self): | ||
| return F.can_attach_to_footprint_via_pinmap( | ||
| pinmap={ | ||
| "1": self.power_unisolated.lv, | ||
| "2": self.power_unisolated.hv, | ||
| "3": self.power_unisolated.lv, | ||
| "4": self.uart.rx.signal, | ||
| "5": self.read_enable.signal, | ||
| "6": self.write_enable.signal, | ||
| "7": self.uart.tx.signal, | ||
| "8": self.power_unisolated.hv, | ||
| "9": self.power_unisolated.lv, | ||
| "10": self.power_unisolated.lv, | ||
| "11": self.power_isolated_out.lv, | ||
| "12": self.power_isolated_out.hv, | ||
| "13": self.rs485.diff_pair.p.signal, | ||
| "14": self.power_isolated_out.lv, | ||
| "15": self.rs485.diff_pair.n.signal, | ||
| "16": self.power_isolated_out.lv, | ||
| "17": self.rs485.diff_pair.n.signal, | ||
| "18": self.rs485.diff_pair.p.signal, | ||
| "19": self.power_isolated_in.hv, | ||
| "20": self.power_isolated_out.lv, | ||
| } | ||
| ) | ||
|
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||
| @L.rt_field | ||
| def pin_association_heuristic(self): | ||
| return F.has_pin_association_heuristic_lookup_table( | ||
| mapping={ | ||
| self.rs485.diff_pair.p.signal: ["A"], | ||
| self.rs485.diff_pair.n.signal: ["B"], | ||
| self.write_enable.signal: ["DE"], | ||
| self.power_unisolated.lv: ["GND1"], | ||
| self.power_isolated_out.lv: ["GND2"], | ||
| self.read_enable.signal: ["RE#"], | ||
| self.uart.rx.signal: ["RXD"], | ||
| self.uart.tx.signal: ["TXD"], | ||
| self.power_unisolated.hv: ["VCC"], | ||
| self.power_isolated_in.hv: ["VISOIN"], | ||
| self.power_isolated_out.hv: ["VISOOUT"], | ||
| self.rs485.diff_pair.p.signal: ["Y"], | ||
| self.rs485.diff_pair.n.signal: ["Z"], | ||
| }, | ||
| accept_prefix=False, | ||
| case_sensitive=False, | ||
| ) | ||
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| def __init__(self, full_duplex: bool = False): | ||
| self._full_duplex = full_duplex | ||
| if full_duplex: | ||
| raise NotImplementedError("Full duplex RS485 not implemented") | ||
|
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| def __preinit__(self): | ||
| # ------------------------------------ | ||
| # connections | ||
| # ------------------------------------ | ||
|
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| # ------------------------------------ | ||
| # parametrization | ||
| # ------------------------------------ | ||
| self.power_isolated_out.voltage.merge(F.Range.from_center_rel(3.3 * P.V, 0.1)) | ||
| self.power_unisolated.voltage.merge(F.Range(3.3 * P.V, 5 * P.V)) | ||
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| F.ElectricLogic.connect_all_module_references( | ||
| self, | ||
| exclude=[ | ||
| self.power_unisolated, | ||
| self.uart, | ||
| self.read_enable, | ||
| self.write_enable, | ||
| ], | ||
| ) | ||
|
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| # TODO: ugly | ||
| self.rs485.diff_pair.n.reference.connect(self.power_isolated_out) | ||
| self.rs485.diff_pair.p.reference.connect(self.power_isolated_out) |
87 changes: 87 additions & 0 deletions
87
src/faebryk/library/Analog_Devices_ADM2587EBRWZ_ReferenceDesign.py
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,87 @@ | ||
| # This file is part of the faebryk project | ||
| # SPDX-License-Identifier: MIT | ||
|
|
||
| import itertools | ||
| import logging | ||
|
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||
| import faebryk.library._F as F # noqa: F401 | ||
| from faebryk.core.module import Module | ||
| from faebryk.libs.library import L # noqa: F401 | ||
| from faebryk.libs.units import P # noqa: F401 | ||
|
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| logger = logging.getLogger(__name__) | ||
|
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| class Analog_Devices_ADM2587EBRWZ_ReferenceDesign(Module): | ||
| """ | ||
| Reference implementation of ADM2587EBRWZ isolated RS485 transceiver | ||
| """ | ||
|
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| # ---------------------------------------- | ||
| # modules, interfaces, parameters | ||
| # ---------------------------------------- | ||
| transceiver = L.f_field(F.Analog_Devices_ADM2587EBRWZ)(full_duplex=False) | ||
|
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| # ---------------------------------------- | ||
| # traits | ||
| # ---------------------------------------- | ||
| @L.rt_field | ||
| def pcb_layout(self): | ||
| from faebryk.exporters.pcb.layout.absolute import LayoutAbsolute | ||
| from faebryk.exporters.pcb.layout.typehierarchy import LayoutTypeHierarchy | ||
|
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| Point = F.has_pcb_position.Point | ||
| L = F.has_pcb_position.layer_type | ||
| LVL = LayoutTypeHierarchy.Level | ||
|
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| return F.has_pcb_layout_defined( | ||
| layout=LayoutTypeHierarchy( | ||
| layouts=[ | ||
| LVL( | ||
| mod_type=F.Analog_Devices_ADM2587EBRWZ, | ||
| layout=LayoutAbsolute(Point((0, 0, 0, L.NONE))), | ||
| ), | ||
| ] | ||
| ) | ||
| ) | ||
|
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| def __preinit__(self): | ||
| # ------------------------------------ | ||
| # connections | ||
| # ------------------------------------ | ||
| self.transceiver.power_isolated_in.connect(self.transceiver.power_isolated_out) | ||
|
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| # ------------------------------------ | ||
| # parametrization | ||
| # ------------------------------------ | ||
| # decoupling unisolated power | ||
| power_unisolated_capacitors = ( | ||
| self.transceiver.power_unisolated.decoupled.decouple() | ||
| .specialize(F.MultiCapacitor(4)) | ||
| .capacitors | ||
| ) | ||
| capacitance_values = [100, 10] # in nF | ||
|
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||
| for cap, value in zip( | ||
| power_unisolated_capacitors, itertools.cycle(capacitance_values) | ||
| ): | ||
| cap.capacitance.merge(F.Range.from_center_rel(value * P.nF, 0.05)) | ||
|
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| # decoupling isolated power in | ||
| for i, cap in enumerate( | ||
| self.transceiver.power_isolated_in.decoupled.decouple() | ||
| .specialize(F.MultiCapacitor(2)) | ||
| .capacitors | ||
| ): | ||
| cap.capacitance.merge( | ||
| F.Range.from_center_rel(capacitance_values[i] * P.nF, 0.05) | ||
| ) | ||
| # decoupling isolated power out | ||
| for i, cap in enumerate( | ||
| self.transceiver.power_isolated_out.decoupled.decouple() | ||
| .specialize(F.MultiCapacitor(2)) | ||
| .capacitors | ||
| ): | ||
| cap.capacitance.merge( | ||
| F.Range.from_center_rel(capacitance_values[i] * P.nF, 0.05) | ||
| ) |
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