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rock-3a:add u-boot image for sata boot
Signed-off-by: pykpkg47 <[email protected]>
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patch/u-boot/legacy/u-boot-radxa-rk35xx/board_rock-3a/add-m2-e-key-sata-boot.patch
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From 464932b87d1e4b518c09378191b5ce9d088e373e Mon Sep 17 00:00:00 2001 | ||
From: pykpkg47 <[email protected]> | ||
Date: Thu, 5 Sep 2024 11:57:55 +0000 | ||
Subject: [PATCH 1/2] arm: dts: rockchip: add rock 3a m.2 e-key sata dts | ||
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||
Signed-off-by: pykpkg47 <[email protected]> | ||
--- | ||
arch/arm/dts/rk3568-rock-3a-sata.dts | 19 +++++++++++++++++++ | ||
1 file changed, 19 insertions(+) | ||
create mode 100644 arch/arm/dts/rk3568-rock-3a-sata.dts | ||
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diff --git a/arch/arm/dts/rk3568-rock-3a-sata.dts b/arch/arm/dts/rk3568-rock-3a-sata.dts | ||
new file mode 100644 | ||
index 00000000000..d64bce108f0 | ||
--- /dev/null | ||
+++ b/arch/arm/dts/rk3568-rock-3a-sata.dts | ||
@@ -0,0 +1,19 @@ | ||
+/* | ||
+ * SPDX-License-Identifier: GPL-2.0+ | ||
+ * | ||
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd | ||
+ */ | ||
+ | ||
+/dts-v1/; | ||
+#include "rk3568-rock-3a.dts" | ||
+ | ||
+ | ||
+&sata2 { | ||
+ u-boot,dm-pre-reloc; | ||
+ status = "okay"; | ||
+}; | ||
+ | ||
+&pcie2x1 { | ||
+ u-boot,dm-pre-reloc; | ||
+ status = "disabled"; | ||
+}; | ||
\ No newline at end of file | ||
-- | ||
2.46.0 | ||
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From 7a35264e211fe29f02fd4bbca50ac7ddb48efe0f Mon Sep 17 00:00:00 2001 | ||
From: pykpkg47 <[email protected]> | ||
Date: Thu, 5 Sep 2024 12:02:55 +0000 | ||
Subject: [PATCH 2/2] configs: add rock 3a sata defconfig | ||
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||
Signed-off-by: pykpkg47 <[email protected]> | ||
--- | ||
configs/rock-3a-sata-rk3568_defconfig | 239 ++++++++++++++++++++++++++ | ||
1 file changed, 239 insertions(+) | ||
create mode 100644 configs/rock-3a-sata-rk3568_defconfig | ||
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diff --git a/configs/rock-3a-sata-rk3568_defconfig b/configs/rock-3a-sata-rk3568_defconfig | ||
new file mode 100644 | ||
index 00000000000..dd6cd68fa66 | ||
--- /dev/null | ||
+++ b/configs/rock-3a-sata-rk3568_defconfig | ||
@@ -0,0 +1,239 @@ | ||
+CONFIG_ARM=y | ||
+CONFIG_ARCH_ROCKCHIP=y | ||
+CONFIG_SPL_LIBCOMMON_SUPPORT=y | ||
+CONFIG_SPL_LIBGENERIC_SUPPORT=y | ||
+CONFIG_SYS_MALLOC_F_LEN=0x80000 | ||
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh" | ||
+CONFIG_ROCKCHIP_RK3568=y | ||
+CONFIG_ROCKCHIP_FIT_IMAGE=y | ||
+CONFIG_ROCKCHIP_VENDOR_PARTITION=y | ||
+CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y | ||
+CONFIG_ROCKCHIP_NEW_IDB=y | ||
+CONFIG_SPL_SERIAL_SUPPORT=y | ||
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y | ||
+CONFIG_TARGET_EVB_RK3568=y | ||
+CONFIG_SPL_LIBDISK_SUPPORT=y | ||
+CONFIG_SPL_NAND_SUPPORT=y | ||
+CONFIG_SPL_SPI_FLASH_SUPPORT=y | ||
+CONFIG_SPL_SPI_SUPPORT=y | ||
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-rock-3a-sata" | ||
+CONFIG_DEBUG_UART=y | ||
+CONFIG_FIT=y | ||
+CONFIG_FIT_IMAGE_POST_PROCESS=y | ||
+CONFIG_FIT_HW_CRYPTO=y | ||
+CONFIG_SPL_LOAD_FIT=y | ||
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y | ||
+CONFIG_SPL_FIT_HW_CRYPTO=y | ||
+# CONFIG_SPL_SYS_DCACHE_OFF is not set | ||
+CONFIG_BOOTDELAY=0 | ||
+CONFIG_SYS_CONSOLE_INFO_QUIET=y | ||
+# CONFIG_DISPLAY_CPUINFO is not set | ||
+CONFIG_ANDROID_BOOTLOADER=y | ||
+CONFIG_ANDROID_AVB=y | ||
+CONFIG_ANDROID_BOOT_IMAGE_HASH=y | ||
+CONFIG_SPL_BOARD_INIT=y | ||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set | ||
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set | ||
+CONFIG_SPL_SEPARATE_BSS=y | ||
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y | ||
+CONFIG_SPL_SHA256_SUPPORT=y | ||
+CONFIG_SPL_CRYPTO_SUPPORT=y | ||
+CONFIG_SPL_HASH_SUPPORT=y | ||
+CONFIG_SPL_MTD_SUPPORT=y | ||
+CONFIG_SPL_ATF=y | ||
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y | ||
+CONFIG_SPL_AB=y | ||
+CONFIG_FASTBOOT_BUF_ADDR=0xc00800 | ||
+CONFIG_FASTBOOT_BUF_SIZE=0x04000000 | ||
+CONFIG_FASTBOOT_FLASH=y | ||
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0 | ||
+CONFIG_CMD_BOOTZ=y | ||
+CONFIG_CMD_DTIMG=y | ||
+# CONFIG_CMD_ELF is not set | ||
+# CONFIG_CMD_IMI is not set | ||
+# CONFIG_CMD_IMLS is not set | ||
+# CONFIG_CMD_XIMG is not set | ||
+# CONFIG_CMD_LZMADEC is not set | ||
+# CONFIG_CMD_UNZIP is not set | ||
+# CONFIG_CMD_FLASH is not set | ||
+# CONFIG_CMD_FPGA is not set | ||
+CONFIG_CMD_GPT=y | ||
+# CONFIG_CMD_LOADB is not set | ||
+# CONFIG_CMD_LOADS is not set | ||
+CONFIG_CMD_BOOT_ANDROID=y | ||
+CONFIG_CMD_BOOT_ROCKCHIP=y | ||
+CONFIG_CMD_MMC=y | ||
+CONFIG_CMD_MTD=y | ||
+CONFIG_CMD_NAND=y | ||
+CONFIG_CMD_PCI=y | ||
+CONFIG_CMD_USB=y | ||
+CONFIG_CMD_USB_MASS_STORAGE=y | ||
+# CONFIG_CMD_ITEST is not set | ||
+# CONFIG_CMD_SETEXPR is not set | ||
+CONFIG_CMD_TFTPPUT=y | ||
+CONFIG_CMD_TFTP_BOOTM=y | ||
+CONFIG_CMD_TFTP_FLASH=y | ||
+# CONFIG_CMD_MISC is not set | ||
+# CONFIG_CMD_CHARGE_DISPLAY is not set | ||
+CONFIG_CMD_MTD_BLK=y | ||
+# CONFIG_SPL_DOS_PARTITION is not set | ||
+# CONFIG_ISO_PARTITION is not set | ||
+CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 | ||
+CONFIG_SPL_OF_CONTROL=y | ||
+CONFIG_SPL_DTB_MINIMUM=y | ||
+CONFIG_OF_LIVE=y | ||
+CONFIG_OF_SPL_REMOVE_PROPS="" | ||
+# CONFIG_NET_TFTP_VARS is not set | ||
+CONFIG_REGMAP=y | ||
+CONFIG_SPL_REGMAP=y | ||
+CONFIG_SYSCON=y | ||
+CONFIG_SPL_SYSCON=y | ||
+CONFIG_CLK=y | ||
+CONFIG_SPL_CLK=y | ||
+CONFIG_CLK_SCMI=y | ||
+CONFIG_DM_CRYPTO=y | ||
+CONFIG_SPL_DM_CRYPTO=y | ||
+CONFIG_ROCKCHIP_CRYPTO_V2=y | ||
+CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y | ||
+CONFIG_DM_RNG=y | ||
+CONFIG_RNG_ROCKCHIP=y | ||
+CONFIG_SCMI_FIRMWARE=y | ||
+CONFIG_ROCKCHIP_GPIO=y | ||
+CONFIG_ROCKCHIP_GPIO_V2=y | ||
+CONFIG_SYS_I2C_ROCKCHIP=y | ||
+CONFIG_DM_KEY=y | ||
+CONFIG_RK8XX_PWRKEY=y | ||
+CONFIG_ADC_KEY=y | ||
+CONFIG_MISC=y | ||
+CONFIG_SPL_MISC=y | ||
+CONFIG_ROCKCHIP_OTP=y | ||
+CONFIG_SPL_ROCKCHIP_SECURE_OTP=y | ||
+CONFIG_MMC_DW=y | ||
+CONFIG_MMC_DW_ROCKCHIP=y | ||
+CONFIG_MMC_SDHCI=y | ||
+CONFIG_MMC_SDHCI_SDMA=y | ||
+CONFIG_MMC_SDHCI_ROCKCHIP=y | ||
+CONFIG_MTD=y | ||
+CONFIG_MTD_BLK=y | ||
+CONFIG_MTD_DEVICE=y | ||
+CONFIG_NAND=y | ||
+CONFIG_NAND_ROCKCHIP_V9=y | ||
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y | ||
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x8000 | ||
+CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x10000 | ||
+CONFIG_MTD_SPI_NAND=y | ||
+CONFIG_SPI_FLASH=y | ||
+CONFIG_SF_DEFAULT_SPEED=20000000 | ||
+CONFIG_SPI_FLASH_EON=y | ||
+CONFIG_SPI_FLASH_GIGADEVICE=y | ||
+CONFIG_SPI_FLASH_MACRONIX=y | ||
+CONFIG_SPI_FLASH_WINBOND=y | ||
+CONFIG_SPI_FLASH_XMC=y | ||
+CONFIG_SPI_FLASH_MTD=y | ||
+CONFIG_DM_ETH=y | ||
+CONFIG_DM_ETH_PHY=y | ||
+CONFIG_DWC_ETH_QOS=y | ||
+CONFIG_GMAC_ROCKCHIP=y | ||
+CONFIG_NVME=y | ||
+CONFIG_PCI=y | ||
+CONFIG_DM_PCI=y | ||
+CONFIG_DM_PCI_COMPAT=y | ||
+CONFIG_PCIE_DW_ROCKCHIP=y | ||
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y | ||
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y | ||
+CONFIG_PHY_ROCKCHIP_NANENG_EDP=y | ||
+CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y | ||
+CONFIG_PINCTRL=y | ||
+CONFIG_SPL_PINCTRL=y | ||
+CONFIG_DM_FUEL_GAUGE=y | ||
+CONFIG_POWER_FG_RK817=y | ||
+CONFIG_IO_DOMAIN=y | ||
+CONFIG_ROCKCHIP_IO_DOMAIN=y | ||
+CONFIG_DM_PMIC=y | ||
+CONFIG_PMIC_RK8XX=y | ||
+CONFIG_REGULATOR_FAN53555=y | ||
+CONFIG_REGULATOR_PWM=y | ||
+CONFIG_DM_REGULATOR_FIXED=y | ||
+CONFIG_DM_REGULATOR_GPIO=y | ||
+CONFIG_REGULATOR_RK8XX=y | ||
+CONFIG_DM_CHARGE_DISPLAY=y | ||
+CONFIG_CHARGE_ANIMATION=y | ||
+CONFIG_PWM_ROCKCHIP=y | ||
+CONFIG_RAM=y | ||
+CONFIG_SPL_RAM=y | ||
+CONFIG_TPL_RAM=y | ||
+CONFIG_DM_RAMDISK=y | ||
+CONFIG_RAMDISK_RO=y | ||
+CONFIG_DM_DMC=y | ||
+CONFIG_ROCKCHIP_DMC_FSP=y | ||
+CONFIG_ROCKCHIP_SDRAM_COMMON=y | ||
+CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0 | ||
+CONFIG_DM_RESET=y | ||
+CONFIG_SPL_DM_RESET=y | ||
+CONFIG_SPL_RESET_ROCKCHIP=y | ||
+CONFIG_BAUDRATE=1500000 | ||
+CONFIG_DEBUG_UART_BASE=0xFE660000 | ||
+CONFIG_DEBUG_UART_CLOCK=24000000 | ||
+CONFIG_DEBUG_UART_SHIFT=2 | ||
+CONFIG_ROCKCHIP_SFC=y | ||
+CONFIG_SYSRESET=y | ||
+CONFIG_USB=y | ||
+CONFIG_USB_XHCI_HCD=y | ||
+CONFIG_USB_XHCI_DWC3=y | ||
+CONFIG_USB_EHCI_HCD=y | ||
+CONFIG_USB_EHCI_GENERIC=y | ||
+CONFIG_USB_OHCI_HCD=y | ||
+CONFIG_USB_OHCI_GENERIC=y | ||
+CONFIG_USB_DWC3=y | ||
+CONFIG_USB_DWC3_GADGET=y | ||
+CONFIG_USB_DWC3_GENERIC=y | ||
+CONFIG_USB_STORAGE=y | ||
+CONFIG_USB_GADGET=y | ||
+CONFIG_USB_GADGET_MANUFACTURER="Rockchip" | ||
+CONFIG_USB_GADGET_VENDOR_NUM=0x2207 | ||
+CONFIG_USB_GADGET_PRODUCT_NUM=0x350a | ||
+CONFIG_USB_GADGET_DOWNLOAD=y | ||
+CONFIG_DM_VIDEO=y | ||
+CONFIG_DISPLAY=y | ||
+CONFIG_DRM_ROCKCHIP=y | ||
+CONFIG_DRM_ROCKCHIP_DW_HDMI=y | ||
+CONFIG_DRM_ROCKCHIP_INNO_MIPI_PHY=y | ||
+CONFIG_DRM_ROCKCHIP_INNO_VIDEO_COMBO_PHY=y | ||
+CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI=y | ||
+CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y | ||
+CONFIG_DRM_ROCKCHIP_LVDS=y | ||
+CONFIG_DRM_ROCKCHIP_RGB=y | ||
+CONFIG_ROCKCHIP_CUBIC_LUT_SIZE=9 | ||
+CONFIG_LCD=y | ||
+CONFIG_USE_TINY_PRINTF=y | ||
+CONFIG_SPL_TINY_MEMSET=y | ||
+CONFIG_RSA=y | ||
+CONFIG_SPL_RSA=y | ||
+CONFIG_RSA_N_SIZE=0x200 | ||
+CONFIG_RSA_E_SIZE=0x10 | ||
+CONFIG_RSA_C_SIZE=0x20 | ||
+CONFIG_XBC=y | ||
+CONFIG_SHA512=y | ||
+CONFIG_LZ4=y | ||
+CONFIG_LZMA=y | ||
+CONFIG_SPL_GZIP=y | ||
+CONFIG_ERRNO_STR=y | ||
+# CONFIG_EFI_LOADER is not set | ||
+CONFIG_AVB_LIBAVB=y | ||
+CONFIG_AVB_LIBAVB_AB=y | ||
+CONFIG_AVB_LIBAVB_ATX=y | ||
+CONFIG_AVB_LIBAVB_USER=y | ||
+CONFIG_RK_AVB_LIBAVB_USER=y | ||
+CONFIG_OPTEE_CLIENT=y | ||
+CONFIG_OPTEE_V2=y | ||
+CONFIG_AHCI=y | ||
+CONFIG_CMD_SCSI=y | ||
+CONFIG_CMD_SATA=y | ||
+CONFIG_DM_SCSI=y | ||
+CONFIG_DWC_AHCI=y | ||
+CONFIG_LIBATA=y | ||
+CONFIG_SATA=y | ||
+CONFIG_SCSI_AHCI=y | ||
+CONFIG_SCSI=y | ||
+CONFIG_SYS_SCSI_MAX_SCSI_ID=1 | ||
+CONFIG_SYS_SCSI_MAX_LUN=1 | ||
-- | ||
2.46.0 |