[feat] Add loongarch64 support #225

yfblock · 2025-02-17T18:57:40Z

Related PR:

yfblock · 2025-02-17T19:43:54Z

基于arceos-org/page_table_multiarch#12 运行 arceos-org/arceos-apps#7:

yfblock · 2025-02-17T19:46:41Z

运行 Starry-next:

Azure-stars · 2025-02-19T08:08:34Z

Please fix the error from la64 ci-test.

yfblock · 2025-02-19T10:12:17Z

Please fix the error from la64 ci-test.

Need new version of arceos-apps, but haven't merged。

Azure-stars · 2025-02-19T10:15:32Z

Please fix the error from la64 ci-test.

Need new version of arceos-apps, but haven't merged it yet!

You can modify https://github.com/arceos-org/arceos/blob/main/.github/workflows/test.yml#L8 to choose a suitable commit of arceos-apps, not need to care whether the PR in arceoes-apps has been merged.

yfblock · 2025-02-19T10:47:32Z

Please fix the error from la64 ci-test.

Need new version of arceos-apps, but haven't merged it yet!

You can modify https://github.com/arceos-org/arceos/blob/main/.github/workflows/test.yml#L8 to choose a suitable commit of arceos-apps, not need to care whether the PR in arceoes-apps has been merged.

Unfortunately, that doesn't solve the problem.

yfblock · 2025-02-19T17:18:30Z

I migrated arceos-apps and arceos to oscomp and then changed the dependency

DownStream CI: https://github.com/oscomp/arceos/actions/runs/13418318407

ulib/axlibc/src/setjmp.rs

equation314 · 2025-02-20T02:19:31Z

.github/workflows/actions/setup-musl/action.yml

+    run: |
+      TOOLCHAIN_REPO=https://github.com/LoongsonLab/oscomp-toolchains-for-oskernel
+      wget ${TOOLCHAIN_REPO}/releases/download/gcc-13.2.0-loongarch64/gcc-13.2.0-loongarch64-linux-gnu.tgz
+      wget ${TOOLCHAIN_REPO}/raw/refs/heads/main/musl-loongarch64-1.2.2.tgz


Why we need to download both gnu and musl toolchain?

This musl is just a warpper

#!/bin/sh MUSL_DIR=$(cd $(dirname $0)/..; pwd) exec "${REALGCC:-loongarch64-linux-gnu-gcc}" "$@" -specs "${MUSL_DIR}/lib/musl-gcc.specs"

modules/axhal/src/platform/loongarch64_qemu_virt/boot.rs

equation314 · 2025-02-20T02:40:22Z

modules/axhal/src/platform/loongarch64_qemu_virt/mp.rs

+    }
+    let stack_top_virt_addr = phys_to_virt(stack_top).as_usize();
+    unsafe {
+        SMP_BOOT_STACK_TOP = stack_top_virt_addr;


Cloud this global variable access be avoided? Could the stack pointer be passed through the mailbox argument?

That's how linux does it. https://github.com/torvalds/linux/blob/87a132e73910e8689902aed7f2fc229d6908383b/arch/loongarch/kernel/smp.c#L347-L360

modules/axhal/src/cpu.rs

equation314 · 2025-02-20T02:45:29Z

modules/axhal/linker.lds.S

@@ -68,7 +68,7 @@ SECTIONS
    . = ALIGN(4K);
    _edata = .;

-    .bss : ALIGN(4K) {


Why need this change?

The difference is the lma in the .bss section.

Added

Sections: Idx Name Size VMA LMA Type 0 00000000 0000000000000000 0000000000000000 1 .text 0000f000 ffff000080000000 ffff000080000000 TEXT 2 .rodata 00003c80 ffff00008000f000 ffff00008000f000 DATA 3 .init_array 00000000 ffff000080012c80 ffff000080012c80 4 .data 00002018 ffff000080013000 ffff000080013000 DATA 5 .tdata 00000000 ffff000080015020 ffff000080015020 DATA 6 .tbss 00000000 ffff000080015020 ffff000080015020 DATA 7 linkme_IRQ 00000000 ffff000080015020 ffff000080015020 DATA 8 linkm2_IRQ 00000008 ffff000080015020 ffff000080015020 DATA 9 linkme_PAGE_FAULT 00000000 ffff000080015028 ffff000080015028 DATA 10 linkm2_PAGE_FAULT 00000008 ffff000080015028 ffff000080015028 DATA 11 .percpu 00000040 0000000000000000 ffff000080016000 DATA 12 .bss 00044000 ffff000080017000 ffff000080017000 BSS 13 .symtab 000011d0 0000000000000000 0000000000000000 14 .shstrtab 0000008f 0000000000000000 0000000000000000 15 .strtab 0000273a 0000000000000000 0000000000000000

Not Added

Sections: Idx Name Size VMA LMA Type 0 00000000 0000000000000000 0000000000000000 1 .text 0000f000 ffff000080000000 ffff000080000000 TEXT 2 .rodata 00003c78 ffff00008000f000 ffff00008000f000 DATA 3 .init_array 00000000 ffff000080012c80 ffff000080012c80 4 .data 00002018 ffff000080013000 ffff000080013000 DATA 5 .tdata 00000000 ffff000080015020 ffff000080015020 DATA 6 .tbss 00000000 ffff000080015020 ffff000080015020 DATA 7 linkme_IRQ 00000000 ffff000080015020 ffff000080015020 DATA 8 linkm2_IRQ 00000008 ffff000080015020 ffff000080015020 DATA 9 linkme_PAGE_FAULT 00000000 ffff000080015028 ffff000080015028 DATA 10 linkm2_PAGE_FAULT 00000008 ffff000080015028 ffff000080015028 DATA 11 .percpu 00000040 0000000000000000 ffff000080016000 DATA 12 .bss 00044000 ffff000080017000 fffe00010002d000 BSS 13 .symtab 000011d0 0000000000000000 0000000000000000 14 .shstrtab 0000008f 0000000000000000 0000000000000000 15 .strtab 0000273a 0000000000000000 0000000000000000

If not added will display:

qemu-system-loongarch64: could not load kernel 'examples/helloworld/helloworld_loongarch64-qemu-virt.elf': The image segments are too big to load

equation314 · 2025-02-24T08:12:30Z

modules/axhal/src/arch/loongarch64/context.rs

@@ -0,0 +1,286 @@
+use core::arch::naked_asm;
+use memory_addr::VirtAddr;
+/// Saved registers when a trap (interrupt or exception) occurs.


Add blank line

equation314 · 2025-02-24T08:15:09Z

modules/axhal/src/arch/loongarch64/context.rs

+#[derive(Debug, Default, Clone, Copy)]
+pub struct TrapFrame {
+    /// All general registers.
+    pub regs: [usize; 32],


I recommend listing all register names like a0, s0 (same as riscv), which avoids magic register offset such as regs[4].

equation314 · 2025-02-24T08:15:52Z

modules/axhal/src/arch/loongarch64/context.rs

+
+                ld.d      $sp, $sp, 3*8       // user sp
+                ertn
+                ",


Instead of having the inline asm code end with a single " line, we can move the " to the end of the last line.

Same for many places.

equation314 · 2025-02-24T11:17:16Z

modules/axhal/src/arch/loongarch64/mod.rs

+    tlbrehi::set_ps(PS_4K);
+
+    // Set Page table entry width
+    pwcl::set_pte_width(8);


Why not use LA64MetaData::PWCL_VALUE

equation314 · 2025-02-24T11:18:23Z

modules/axhal/src/arch/loongarch64/mod.rs

+/// Initializes CPU states on the current CPU.
+pub fn cpu_init() {
+    // Enable floating point
+    euen::set_fpe(true);


Enable FP conditionally with the fp_simd feature.

equation314 · 2025-02-24T11:23:35Z

modules/axhal/src/arch/loongarch64/trap.S

+.endm
+
+.macro RESTORE_REGS
+    csrrd   $t0, 0x1


Why not use .equ PRMD, 0x1

equation314 · 2025-02-24T11:23:55Z

modules/axhal/src/arch/loongarch64/trap.S

+    ld.d    $s7, $sp, 30*8
+    ld.d    $s8, $sp, 31*8
+.endm
+


Remove blank line

equation314 · 2025-02-24T11:26:05Z

scripts/make/qemu.mk

@@ -21,6 +21,9 @@ else ifeq ($(ARCH), aarch64)
  else
    machine := virt
  endif
+else ifeq ($(ARCH), loongarch64)
+  machine := virt
+  override MEM := 1G


Why it requires 1G memory?

equation314 · 2025-02-24T11:31:20Z

modules/axhal/src/arch/loongarch64/context.rs

+    /// Exception Return Address
+    pub era: usize,
+    /// Access Memory Address When Exception
+    pub badv: usize,


badv and crmd don't need to be saved in TrapFrame, do they? We can use csrrd to get them when we need them.

equation314 · 2025-02-24T11:32:05Z

modules/axhal/src/arch/loongarch64/context.rs

+        unsafe {
+            core::arch::asm!(
+                r"
+                .equ KSAVE_KSP,    0x30


Put the common .equ definition and the ld.d sequence into a macro, like include_asm_macros in riscv.

equation314 · 2025-02-25T15:22:05Z

modules/axhal/src/arch/loongarch64/context.rs

+
+        super::disable_irqs();
+        prmd::set_pplv(CpuMode::Ring3);
+        prmd::set_pie(true);


Why not write self.prmd to the actual CSR.PRMD?

equation314 · 2025-02-25T15:39:12Z

modules/axhal/src/arch/loongarch64/context.rs

+
+impl TaskContext {
+    /// Creates a new default context for a new task.
+    pub const fn new() -> Self {


TaskContext::new does not require const, use safe code instead.

equation314 · 2025-02-25T15:41:56Z

modules/axhal/src/arch/loongarch64/context.rs

+    pub s: [usize; 10], // loongArch need to save 10 static registers from $r22 to $r31
+    pub tp: usize,
+    #[cfg(feature = "uspace")]
+    pub pgdl: usize,


Add comments to indicate it's the user page table root.

equation314 · 2025-02-25T15:42:47Z

modules/axhal/src/arch/loongarch64/context.rs

+        self.tp = tls_area.as_usize();
+    }
+
+    /// Changes the page table root (`pgdl` register for loongarch64).


Comments not matched

equation314 · 2025-02-25T15:46:00Z

modules/axhal/src/arch/loongarch64/context.rs

+
+            // restore new context
+            ld.d     $ra, $a1, 0
+            ld.d     $s0, $a1, 2 * 8


Adjust the restore order: fp, s8, ..., s0, sp, ra

equation314 · 2025-02-25T16:16:12Z

modules/axhal/src/platform/loongarch64_qemu_virt/time.rs

@@ -0,0 +1,62 @@
+use loongArch64::time::Time;
+
+const NANOS_PER_TICK: u64 = crate::time::NANOS_PER_SEC / axconfig::devices::TIMER_FREQUENCY as u64;


Get timer frequency by loongArch64::time::get_timer_freq?

equation314 · 2025-02-25T16:21:23Z

modules/axhal/src/platform/loongarch64_qemu_virt/time.rs

+    let init_value = ticks_deadline - ticks_now;
+
+    // This initial value must be an integer multiple of 4.
+    tcfg::set_init_val(((init_value + 3) & !3) as _);


The alignment of init_value is unnecessary, its lowest two bits are simply ignored.

equation314 · 2025-02-25T16:21:57Z

modules/axhal/src/platform/loongarch64_qemu_virt/time.rs

+
+    // This initial value must be an integer multiple of 4.
+    tcfg::set_init_val(((init_value + 3) & !3) as _);
+    tcfg::set_periodic(false);


Setting periodic and en again is also unnecessary.

equation314 · 2025-02-25T16:34:08Z

modules/axhal/src/platform/loongarch64_qemu_virt/irq.rs

+/// The timer IRQ number.
+pub const TIMER_IRQ_NUM: usize = 11;
+
+static TIMER_HANDLER: LazyInit<IrqHandler> = LazyInit::new();


Hardware interrupts and timer interrupts are numbered together in la64, so we can manage them uniformly with axhal::irq::IRQ_HANDLER_TABLE. The separate TIMER_HANDLER is unnecessary.

equation314 · 2025-02-25T16:34:41Z

modules/axhal/src/platform/loongarch64_qemu_virt/irq.rs

+pub const EXT_IRQ_NUM: usize = 2;
+
+/// The timer IRQ number.
+pub const TIMER_IRQ_NUM: usize = 11;


Get it from estat::Interrupt::Timer

yfblock force-pushed the main branch from 263abf0 to 1f4ee80 Compare February 17, 2025 19:12

yfblock force-pushed the main branch from 1f4ee80 to 2854af8 Compare February 18, 2025 09:25

chyyuu requested review from Azure-stars, equation314 and hky1999 February 19, 2025 08:04

yfblock force-pushed the main branch 2 times, most recently from 71c524a to ae31649 Compare February 19, 2025 10:46

yfblock force-pushed the main branch from ae31649 to 8480a4f Compare February 19, 2025 17:00

equation314 reviewed Feb 20, 2025

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modules/axhal/src/cpu.rs Outdated Show resolved Hide resolved

equation314 reviewed Feb 20, 2025

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feat: add loongarch64 support

949dc71

yfblock force-pushed the main branch from 8480a4f to 949dc71 Compare February 20, 2025 07:10

equation314 reviewed Feb 24, 2025

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equation314 reviewed Feb 25, 2025

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		@@ -0,0 +1,62 @@
		use loongArch64::time::Time;

		const NANOS_PER_TICK: u64 = crate::time::NANOS_PER_SEC / axconfig::devices::TIMER_FREQUENCY as u64;

[feat] Add loongarch64 support #225

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[feat] Add loongarch64 support #225

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yfblock commented Feb 17, 2025 • edited Loading

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yfblock commented Feb 17, 2025 •

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yfblock commented Feb 19, 2025 •

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equation314 Feb 24, 2025 •

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