[WIP] Add ASIC Flow #8
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Signed-off-by: Pawel Czarnecki <[email protected]>
Signed-off-by: Pawel Czarnecki <[email protected]>
Signed-off-by: Pawel Czarnecki <[email protected]>
Add OpenROAD-flow-scripts dependencies Add Makefile targets for simple flow test Signed-off-by: Pawel Czarnecki <[email protected]>
Signed-off-by: Pawel Czarnecki <[email protected]>
Signed-off-by: Pawel Czarnecki <[email protected]>
Add build target and simple verification target for Yosys, Surelog and Yosys Plugins Signed-off-by: Pawel Czarnecki <[email protected]>
Signed-off-by: Pawel Czarnecki <[email protected]>
Add config files for OpenROAD-flow-scripts for implementing physical design in SKY130 and ASAP7 technologies. Signed-off-by: Pawel Czarnecki <[email protected]>
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Signed-off-by: Pawel Czarnecki <[email protected]>
Signed-off-by: Pawel Czarnecki <[email protected]>
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Signed-off-by: Pawel Czarnecki <[email protected]>
Signed-off-by: Pawel Czarnecki <[email protected]>
Signed-off-by: Pawel Czarnecki <[email protected]>
Signed-off-by: Pawel Czarnecki <[email protected]>
Signed-off-by: Pawel Czarnecki <[email protected]>
Signed-off-by: Pawel Czarnecki <[email protected]>
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| module counter ( | ||
| output reg [10:0] out, | ||
| input wire enable, | ||
| input wire clk, | ||
| input wire reset |
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[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| module counter ( | |
| output reg [10:0] out, | |
| input wire enable, | |
| input wire clk, | |
| input wire reset | |
| module counter ( | |
| output reg [10:0] out, | |
| input wire enable, | |
| input wire clk, | |
| input wire reset |
| input wire clk, | ||
| input wire reset | ||
| ); | ||
| always_ff @(posedge clk) |
There was a problem hiding this comment.
[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| always_ff @(posedge clk) | |
| always_ff @(posedge clk) |
| ); | ||
| always_ff @(posedge clk) | ||
| if (reset) begin | ||
| out <= 8'b0 ; |
There was a problem hiding this comment.
[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| out <= 8'b0 ; | |
| out <= 8'b0; |
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