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Add unit tests to CI
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Signed-off-by: Rafal Kolucki <[email protected]>
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koluckirafal committed Apr 12, 2023
1 parent bd3615b commit a82cfc1
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Showing 5 changed files with 121 additions and 5 deletions.
113 changes: 113 additions & 0 deletions .github/workflows/verification.yml
Original file line number Diff line number Diff line change
@@ -0,0 +1,113 @@
name: VeeR-EL2 verification

on:
push:
pull_request:

jobs:

verilator:
name: Build Verilator
runs-on: ubuntu-latest
env:
CCACHE_DIR: "/opt/veer-el2/.cache/"
DEBIAN_FRONTEND: "noninteractive"

steps:
- name: Install prerequisities
run: |
sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \
git autoconf automake autotools-dev curl python3 python3-pip \
libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex \
texinfo gperf libtool patchutils bc zlib1g zlib1g-dev libexpat-dev \
ninja-build ccache libfl2 libfl-dev help2man
- name: Create Cache Timestamp
id: cache_timestamp
uses: nanzm/[email protected]
with:
format: 'YYYY-MM-DD-HH-mm-ss'

- name: Setup cache
uses: actions/cache@v2
timeout-minutes: 3
continue-on-error: true
with:
path: "/opt/veer-el2/.cache/"
key: cache_${{ steps.cache_timestamp.outputs.time }}
restore-keys: cache_

- name: Build Verilator
run: |
git clone https://github.com/verilator/verilator
pushd verilator
git checkout v5.008
autoconf
./configure --prefix=/opt/verilator
make -j `nproc`
make install
popd
cd /opt && tar -czvf verilator.tar.gz verilator/
- name: Store Verilator binaries
uses: actions/upload-artifact@v3
with:
name: verilator
path: /opt/*.tar.gz
retention-days: 1

tests:
name: Verification tests
runs-on: ubuntu-latest
needs: verilator
env:
DEBIAN_FRONTEND: "noninteractive"

steps:
- name: Setup repository
uses: actions/checkout@v3
with:
submodules: recursive
path: Caliptra

- name: Setup repository
uses: actions/checkout@v3
with:
submodules: recursive

- name: Install dependencies
run: |
sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \
git python3 python3-pip build-essential ninja-build cpanminus ccache \
gcc-riscv64-unknown-elf
sudo cpanm Bit::Vector
pip3 install meson
pip3 install -r verification/requirements.txt
- name: Download verilator binaries
uses: actions/download-artifact@v3
with:
name: verilator
path: /opt

- name: Unpack verilator binaries
run: |
cd /opt && tar -zxvf verilator.tar.gz
- name: Run tests
run: |
export PATH=/opt/verilator/bin:$PATH
export RV_ROOT=`pwd`
export PYTHONUNBUFFERED=1
$RV_ROOT/configs/veer.config
pytest verification/test.py -v --timeout=480 --html=test.html --html=$GITHUB_STEP_SUMMARY
- name: Pack artifacts
if: always()
uses: actions/upload-artifact@v3
with:
name: results
path: |
test.html
assets/
sim_build/
3 changes: 2 additions & 1 deletion verification/requirements.txt
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@@ -1,4 +1,5 @@
cocotb==1.7.2
cocotb-test==0.2.4
pytest-html
pytest-xdist
pytest-timeout
pytest-md
1 change: 1 addition & 0 deletions verification/test.py
Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,7 @@ def test_exu_alu():

run(
simulator = "verilator",
compile_args = ["-Wno-WIDTH", "-Wno-UNOPTFLAT"],
verilog_sources = ["{}/{}".format(rv_root, el) for el in verilog_sources],
includes = ["{}/{}".format(rv_root, el) for el in includes],
toplevel = "el2_exu_alu_ctl",
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5 changes: 3 additions & 2 deletions verification/tests/common.py
Original file line number Diff line number Diff line change
Expand Up @@ -31,12 +31,13 @@ def __init__(self, dut, **kwargs):
# test_name = kwargs.get('test_name', inspect.stack()[1][3])
# tn = cocotb.binary.BinaryValue(value=test_name.encode(), n_bits=4096)
# self.dut.test_name.value = tn

@cocotb.coroutine
async def reset(self):
self.dut.rst_l.value = 1
await ClockCycles(self.dut.clk, 2)
self.dut.rst_l.value = 0
await ClockCycles(self.dut.clk, 2)
self.dut.rst_l.value = 1
await ClockCycles(self.dut.clk, 2)
await ClockCycles(self.dut.clk, 2)

4 changes: 2 additions & 2 deletions verification/tests/test-exu-alu.py
Original file line number Diff line number Diff line change
Expand Up @@ -24,8 +24,8 @@
async def test_add(dut):
inputs = random.sample(range(0x1, 0x3fffffff), 2)

clk_gen = make_clock(dut, 1)
harness = Harness(dut)
clk_gen = make_clock(harness.dut, 100)

await harness.reset()

Expand All @@ -45,8 +45,8 @@ async def test_add(dut):
async def test_sub(dut):
inputs = random.sample(range(0x1, 0x3fffffff), 2)

clk_gen = make_clock(dut, 1)
harness = Harness(dut)
clk_gen = make_clock(harness.dut, 100)

await harness.reset()

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