fix dma init

app/Kconfig

@@ -17,6 +17,10 @@ config XTENSA_CCOUNT_HZ
 config ZEPHYR_LOG
 	default y
 
+# Used to be selected by the platform, find a home
+config SCHEDULE_DMA_MULTI_CHANNEL
+	default y if SOC_FAMILY_MTK
+
 # SOF code assumes system work queue and other system
 # wide threads are pinned to a single core.
 # CPU_MASK_PIN_ONLY must be set for all SOF builds.

src/platform/mtk/include/platform/lib/dma.h

@@ -0,0 +1,11 @@
+#ifndef _SOF_PLATFORM_MTK_DMA_H
+#define _SOF_PLATFORM_MTK_DMA_H
+
+/* Only needed in dma_multi_chan_domain.c */
+#define PLATFORM_NUM_DMACS 2
+#define PLATFORM_MAX_DMA_CHAN 32
+
+#define dma_chan_irq(dma, chan)		dma_irq(dma)
+#define dma_chan_irq_name(dma, chan)	dma_irq_name(dma)
+
+#endif /* _SOF_PLATFORM_MTK_DMA_H */

src/platform/mtk/platform.c

@@ -114,6 +114,14 @@ static int set_cpuclk(int clock, int hz)
 	return clock == 0 && hz == CONFIG_XTENSA_CCOUNT_HZ ? 0 : -EINVAL;
 }
 
+void interrupt_clear_mask(uint32_t irq, uint32_t mask)
+{
+	/* This is required out of dma_multi_chan_domain but nothing
+	 * defines it in Zephyr builds.  Stub with a noop here,
+	 * knowing that MTK DMA devices don't have interrupts.
+	 */
+}
+
 /* Dummy CPU clock driver that supports one known frequency.  This
  * hardware has clock scaling support, but it hasn't historically been
  * exercised so we have nothing to test against.
@@ -142,6 +150,10 @@ int platform_init(struct sof *sof)
 	mtk_dai_init(sof);
 	scheduler_init_edf();
 	scheduler_init_ll(sof->platform_timer_domain);
+	sof->platform_dma_domain =
+		dma_multi_chan_domain_init(&sof->dma_info->dma_array[0],
+					   sof->dma_info->num_dmas,
+					   PLATFORM_DEFAULT_CLOCK, false);
 	sa_init(sof, CONFIG_SYSTICK_PERIOD);
 	return 0;
 }