In this project we design a simple mips processor in phase one with SystemVerilog and after that we add multicycle memory and cache in phase two and then in phase three we add pipelines to mips machine. in phase four we design a floating-point coprocessor and register file for store floating-point numbers.
In the end, we have written a series of tests to check the correct operation of the processor in the test folder, which you can see in the test folder.
You can see all doucuments about design and codes in documemts.
To run the project, you must have Docker installed on your system.
You can use the project by running these commands in the root of the project.
make assemble: assemble all verilog files.
make compile: compile modules.
make verify [test name]: run specific test.
make verify-all: run all tests.
make clean: delete all compiled moudels.