WIP: Verilator Compatibility

rtl/arbiter.v

@@ -24,6 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+// verilator lint_off WIDTH
+// verilator lint_off LITENDIAN
+
 `resetall
 `timescale 1ns / 1ps
 `default_nettype none

rtl/axil_crossbar_addr.v

@@ -24,6 +24,10 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+// verilator lint_off WIDTH
+// verilator lint_off LITENDIAN
+// verilator lint_off CASEINCOMPLETE
+
 `resetall
 `timescale 1ns / 1ps
 `default_nettype none

rtl/axil_crossbar_rd.v

@@ -24,6 +24,10 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+// verilator lint_off WIDTH
+// verilator lint_off LITENDIAN
+// verilator lint_off UNSIGNED
+
 `resetall
 `timescale 1ns / 1ps
 `default_nettype none

rtl/axil_crossbar_wr.v

@@ -24,6 +24,10 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+// verilator lint_off WIDTH
+// verilator lint_off LITENDIAN
+// verilator lint_off UNSIGNED
+
 `resetall
 `timescale 1ns / 1ps
 `default_nettype none

rtl/priority_encoder.v

@@ -24,6 +24,10 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+// verilator lint_off WIDTH
+// verilator lint_off LITENDIAN
+// verilator lint_off UNOPTFLAT
+
 `resetall
 `timescale 1ns / 1ps
 `default_nettype none

tb/axil_crossbar/test_axil_crossbar.py

@@ -242,9 +242,6 @@ def test_axil_crossbar(request, s_count, m_count, data_width):
 
     parameters = {}
 
-    parameters['S_COUNT'] = s_count
-    parameters['M_COUNT'] = m_count
-
     parameters['DATA_WIDTH'] = data_width
     parameters['ADDR_WIDTH'] = 32
     parameters['STRB_WIDTH'] = parameters['DATA_WIDTH'] // 8