pulley: Get simd_conversions.wast test working

Lots of narrowing/extending/conversion-related opcodes implemented. Note
that these opcodes are all in the "extended" namespace as the 1-byte
namespace has started to overflow.

cranelift/codegen/src/isa/pulley_shared/lower.isle

@@ -160,13 +160,23 @@
 (rule (lower (has_type $I64 (isub a b)))
       (pulley_xsub64 a b))
 
+(rule (lower (has_type $I8X16 (isub a b))) (pulley_vsubi8x16 a b))
+(rule (lower (has_type $I16X8 (isub a b))) (pulley_vsubi16x8 a b))
+(rule (lower (has_type $I32X4 (isub a b))) (pulley_vsubi32x4 a b))
+(rule (lower (has_type $I64X2 (isub a b))) (pulley_vsubi64x2 a b))
+
 ;;;; Rules for `imul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (rule (lower (has_type $I8 (imul a b))) (pulley_xmul32 a b))
 (rule (lower (has_type $I16 (imul a b))) (pulley_xmul32 a b))
 (rule (lower (has_type $I32 (imul a b))) (pulley_xmul32 a b))
 (rule (lower (has_type $I64 (imul a b))) (pulley_xmul64 a b))
 
+(rule (lower (has_type $I8X16 (imul a b))) (pulley_vmuli8x16 a b))
+(rule (lower (has_type $I16X8 (imul a b))) (pulley_vmuli16x8 a b))
+(rule (lower (has_type $I32X4 (imul a b))) (pulley_vmuli32x4 a b))
+(rule (lower (has_type $I64X2 (imul a b))) (pulley_vmuli64x2 a b))
+
 ;;;; Rules for `umulhi` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (rule (lower (has_type $I8 (umulhi a b)))
@@ -703,6 +713,18 @@
 (rule (lower (has_type $F64 (fcvt_from_sint val @ (value_type $I64))))
   (pulley_f64_from_x64_s val))
 
+(rule (lower (has_type $F32X4 (fcvt_from_sint val @ (value_type $I32X4))))
+  (pulley_vf32x4_from_i32x4_s val))
+
+(rule (lower (has_type $F32X4 (fcvt_from_uint val @ (value_type $I32X4))))
+  (pulley_vf32x4_from_i32x4_u val))
+
+(rule (lower (has_type $F64X2 (fcvt_from_sint val @ (value_type $I64X2))))
+  (pulley_vf64x2_from_i64x2_s val))
+
+(rule (lower (has_type $F64X2 (fcvt_from_uint val @ (value_type $I64X2))))
+  (pulley_vf64x2_from_i64x2_u val))
+
 ;;;; Rules for `fcvt_to_{u,s}int_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (rule (lower (has_type $I32 (fcvt_to_uint_sat val @ (value_type $F32))))
@@ -872,3 +894,45 @@
 (rule (lower (vany_true a @ (value_type $I64X2))) (pulley_vanytrue64x2 a))
 (rule (lower (vany_true a @ (value_type $F32X4))) (pulley_vanytrue32x4 a))
 (rule (lower (vany_true a @ (value_type $F64X2))) (pulley_vanytrue64x2 a))
+
+;;;; Rules for `swiden_low` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule (lower (swiden_low a @ (value_type $I8X16))) (pulley_vwidenlow8x16_s a))
+(rule (lower (swiden_low a @ (value_type $I16X8))) (pulley_vwidenlow16x8_s a))
+(rule (lower (swiden_low a @ (value_type $I32X4))) (pulley_vwidenlow32x4_s a))
+
+;;;; Rules for `swiden_high` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule (lower (swiden_high a @ (value_type $I8X16))) (pulley_vwidenhigh8x16_s a))
+(rule (lower (swiden_high a @ (value_type $I16X8))) (pulley_vwidenhigh16x8_s a))
+(rule (lower (swiden_high a @ (value_type $I32X4))) (pulley_vwidenhigh32x4_s a))
+
+;;;; Rules for `uwiden_low` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule (lower (uwiden_low a @ (value_type $I8X16))) (pulley_vwidenlow8x16_u a))
+(rule (lower (uwiden_low a @ (value_type $I16X8))) (pulley_vwidenlow16x8_u a))
+(rule (lower (uwiden_low a @ (value_type $I32X4))) (pulley_vwidenlow32x4_u a))
+
+;;;; Rules for `uwiden_high` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule (lower (uwiden_high a @ (value_type $I8X16))) (pulley_vwidenhigh8x16_u a))
+(rule (lower (uwiden_high a @ (value_type $I16X8))) (pulley_vwidenhigh16x8_u a))
+(rule (lower (uwiden_high a @ (value_type $I32X4))) (pulley_vwidenhigh32x4_u a))
+
+;;;; Rules for `snarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule (lower (snarrow a @ (value_type $I16X8) b)) (pulley_vnarrow16x8_s a b))
+(rule (lower (snarrow a @ (value_type $I32X4) b)) (pulley_vnarrow32x4_s a b))
+
+;;;; Rules for `unarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule (lower (unarrow a @ (value_type $I16X8) b)) (pulley_vnarrow16x8_u a b))
+(rule (lower (unarrow a @ (value_type $I32X4) b)) (pulley_vnarrow32x4_u a b))
+
+;;;; Rules for `fvpromote_low` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule (lower (fvpromote_low a @ (value_type $F32X4))) (pulley_vfpromotelow a))
+
+;;;; Rules for `fvdemote` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule (lower (fvdemote a @ (value_type $F64X2))) (pulley_vfdemote a))

cranelift/filetests/filetests/runtests/simd-fcvt-from-sint.clif

@@ -9,6 +9,10 @@ target x86_64 sse42 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %fcvt_from_sint32(i32x4) -> f32x4 {
 block0(v0: i32x4):

cranelift/filetests/filetests/runtests/simd-fcvt-from-uint.clif

@@ -10,6 +10,10 @@ target x86_64 sse42 has_avx has_avx512vl has_avx512f
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %fcvt_from_uint32(i32x4) -> f32x4 {
 block0(v0: i32x4):

cranelift/filetests/filetests/runtests/simd-fvdemote.clif

@@ -9,6 +9,10 @@ target x86_64 sse42 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %fvdemote(f64x2) -> f32x4 {
 block0(v0: f64x2):

cranelift/filetests/filetests/runtests/simd-fvpromote-low.clif

@@ -9,6 +9,10 @@ target x86_64 sse42 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %fvpromote_low(f32x4) -> f64x2 {
 block0(v0: f32x4):

cranelift/filetests/filetests/runtests/simd-iadd.clif

@@ -7,6 +7,10 @@ target x86_64 skylake
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 
 function %iadd_i8x16(i8x16, i8x16) -> i8x16 {

cranelift/filetests/filetests/runtests/simd-imul-i8x16.clif

@@ -5,6 +5,10 @@ target s390x
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 
 function %imul_i8x16(i8x16, i8x16) -> i8x16 {

cranelift/filetests/filetests/runtests/simd-imul.clif

@@ -7,6 +7,10 @@ target x86_64 skylake
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %imul_i16x8(i16x8, i16x8) -> i16x8 {
 block0(v0:i16x8, v1:i16x8):

cranelift/filetests/filetests/runtests/simd-isub.clif

@@ -7,6 +7,10 @@ target x86_64 skylake
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 
 function %isub_i8x16(i8x16, i8x16) -> i8x16 {

cranelift/filetests/filetests/runtests/simd-snarrow.clif

@@ -7,6 +7,10 @@ target x86_64 has_sse3 has_ssse3 has_sse41 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %snarrow_i16x8(i16x8, i16x8) -> i8x16 {
 block0(v0: i16x8, v1: i16x8):

cranelift/filetests/filetests/runtests/simd-swidenhigh.clif

@@ -9,6 +9,10 @@ target x86_64 sse41 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %swidenhigh_i8x16(i8x16) -> i16x8 {
 block0(v0: i8x16):

cranelift/filetests/filetests/runtests/simd-swidenlow.clif

@@ -8,6 +8,10 @@ target x86_64 sse41 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %swidenlow_i8x16(i8x16) -> i16x8 {
 block0(v0: i8x16):

cranelift/filetests/filetests/runtests/simd-unarrow.clif

@@ -9,6 +9,10 @@ target x86_64 sse42 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %unarrow_i16x8(i16x8, i16x8) -> i8x16 {
 block0(v0: i16x8, v1: i16x8):

cranelift/filetests/filetests/runtests/simd-uwidenhigh.clif

@@ -8,6 +8,10 @@ target x86_64 sse41 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %uwidenhigh_i8x16(i8x16) -> i16x8 {
 block0(v0: i8x16):

cranelift/filetests/filetests/runtests/simd-uwidenlow.clif

@@ -8,6 +8,10 @@ target x86_64 sse41 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %uwidenlow_i8x16(i8x16) -> i16x8 {
 block0(v0: i8x16):

crates/wasmtime/src/runtime/vm/interpreter.rs

@@ -193,6 +193,10 @@ impl InterpreterRef<'_> {
         clippy::cast_sign_loss,
         reason = "macro-generated code"
     )]
+    #[cfg_attr(
+        not(feature = "component-model"),
+        expect(unused_macro_rules, reason = "macro-code")
+    )]
     unsafe fn call_indirect_host(&mut self, id: u8) {
         let id = u32::from(id);
         let fnptr = self.0[XReg::x0].get_ptr::<u8>();

crates/wast-util/src/lib.rs

@@ -402,9 +402,7 @@ impl WastTest {
         if config.compiler == Compiler::CraneliftPulley {
             let unsupported = [
                 "misc_testsuite/memory64/simd.wast",
-                "misc_testsuite/simd/almost-extmul.wast",
                 "misc_testsuite/simd/canonicalize-nan.wast",
-                "misc_testsuite/simd/cvt-from-uint.wast",
                 "misc_testsuite/simd/issue6725-no-egraph-panic.wast",
                 "misc_testsuite/simd/issue_3327_bnot_lowering.wast",
                 "misc_testsuite/simd/replace-lane-preserve.wast",
@@ -428,7 +426,6 @@ impl WastTest {
                 "spec_testsuite/proposals/memory64/i16x8_relaxed_q15mulr_s.wast",
                 "spec_testsuite/proposals/memory64/i32x4_relaxed_trunc.wast",
                 "spec_testsuite/proposals/memory64/i8x16_relaxed_swizzle.wast",
-                "spec_testsuite/simd_conversions.wast",
                 "spec_testsuite/simd_f32x4.wast",
                 "spec_testsuite/simd_f32x4_arith.wast",
                 "spec_testsuite/simd_f32x4_cmp.wast",
@@ -443,26 +440,22 @@ impl WastTest {
                 "spec_testsuite/simd_i16x8_arith2.wast",
                 "spec_testsuite/simd_i16x8_cmp.wast",
                 "spec_testsuite/simd_i16x8_extadd_pairwise_i8x16.wast",
-                "spec_testsuite/simd_i16x8_extmul_i8x16.wast",
                 "spec_testsuite/simd_i16x8_q15mulr_sat_s.wast",
                 "spec_testsuite/simd_i16x8_sat_arith.wast",
                 "spec_testsuite/simd_i32x4_arith.wast",
                 "spec_testsuite/simd_i32x4_arith2.wast",
                 "spec_testsuite/simd_i32x4_cmp.wast",
                 "spec_testsuite/simd_i32x4_dot_i16x8.wast",
                 "spec_testsuite/simd_i32x4_extadd_pairwise_i16x8.wast",
-                "spec_testsuite/simd_i32x4_extmul_i16x8.wast",
                 "spec_testsuite/simd_i32x4_trunc_sat_f32x4.wast",
                 "spec_testsuite/simd_i32x4_trunc_sat_f64x2.wast",
                 "spec_testsuite/simd_i64x2_arith.wast",
                 "spec_testsuite/simd_i64x2_arith2.wast",
                 "spec_testsuite/simd_i64x2_cmp.wast",
-                "spec_testsuite/simd_i64x2_extmul_i32x4.wast",
                 "spec_testsuite/simd_i8x16_arith.wast",
                 "spec_testsuite/simd_i8x16_arith2.wast",
                 "spec_testsuite/simd_i8x16_cmp.wast",
                 "spec_testsuite/simd_i8x16_sat_arith.wast",
-                "spec_testsuite/simd_int_to_int_extend.wast",
                 "spec_testsuite/simd_lane.wast",
                 "spec_testsuite/simd_load.wast",
                 "spec_testsuite/simd_load16_lane.wast",