pulley: Shuffle opcodes to free some 1-byte opcodes

In the near future the set of opcodes here are going to be expanded
along a number of axes such as:

* More modes of addressing loads/stores other than just `reg + offset32`.
* Opcodes with immediate operands rather than unconditional register operands.

The 1-byte opcode namespace is already filling up and there's a bit of a
mishmash of what's 1-byte and what's "extended" for now. To help bridge
this gap in the interim shuffle all float/vector-related opcodes into
the "extended" opcode namespace. This frees up a large chunk of the
1-byte opcode namespace for future expansion with extensions like above.

I'll note that I'm not 100% sure that the opcodes will all stay here
after this reshuffling. I haven't done any profiling/performance
analysis to gauge the impact of this change. The immediate goal is to
start experimenting with non-float/vector programs and get them
profiling well. This will require more "macro opcodes" such as new
addressing modes and opcodes-with-immediates. These are expected to be
relatively hot opcodes and thus probably want to be in the "fast" 1-byte
namespace, hence the shuffling here.

My plan is to in the future do a bit of an evaluation with a
float/vector program and see whether it make sense to shuffle some of
them into this 1-bytecode space as well. More radically it might make
sense to remove the split between ops/extended ops and instead just have
a 2-byte opcode space entirely. That's all left for future evaluations
though.

cranelift/codegen/src/isa/pulley_shared/inst/mod.rs

@@ -485,8 +485,8 @@ where
     }
 
     fn worst_case_size() -> CodeOffset {
-        // `Vconst128 { dst, imm }` is 18 bytes (opcode + dst + 16-byte imm)
-        18
+        // `Vconst128 { dst, imm }` is 20 bytes (3 byte opcode + dst + 16-byte imm)
+        20
     }
 
     fn ref_type_regclass(_settings: &settings::Flags) -> RegClass {