pulley: Implement CLIF lowering of insertlane

Gets some misc wast tests passing.
alexcrichton · Dec 17, 2024 · 21eabb1 · 21eabb1
1 parent e2c22d5
commit 21eabb1
Show file tree

Hide file tree

Showing 5 changed files with 116 additions and 5 deletions.
diff --git a/cranelift/codegen/src/isa/pulley_shared/lower.isle b/cranelift/codegen/src/isa/pulley_shared/lower.isle
@@ -951,3 +951,18 @@
   (pulley_fextractv32x4 a lane))
 (rule (lower (extractlane a @ (value_type $F64X2) (u8_from_uimm8 lane)))
   (pulley_fextractv64x2 a lane))
+
+;;;; Rules for `insertlane` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule (lower (insertlane a @ (value_type $I8X16) b (u8_from_uimm8 lane)))
+  (pulley_vinsertx8 a b lane))
+(rule (lower (insertlane a @ (value_type $I16X8) b (u8_from_uimm8 lane)))
+  (pulley_vinsertx16 a b lane))
+(rule (lower (insertlane a @ (value_type $I32X4) b (u8_from_uimm8 lane)))
+  (pulley_vinsertx32 a b lane))
+(rule (lower (insertlane a @ (value_type $I64X2) b (u8_from_uimm8 lane)))
+  (pulley_vinsertx64 a b lane))
+(rule (lower (insertlane a @ (value_type $F32X4) b (u8_from_uimm8 lane)))
+  (pulley_vinsertf32 a b lane))
+(rule (lower (insertlane a @ (value_type $F64X2) b (u8_from_uimm8 lane)))
+  (pulley_vinsertf64 a b lane))
diff --git a/cranelift/filetests/filetests/runtests/simd-insertlane.clif b/cranelift/filetests/filetests/runtests/simd-insertlane.clif
@@ -9,6 +9,10 @@ target x86_64 sse42 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %insertlane_i8x16_0(i8x16, i8) -> i8x16 {
 block0(v0: i8x16, v1: i8):

diff --git a/crates/wast-util/src/lib.rs b/crates/wast-util/src/lib.rs
@@ -404,7 +404,6 @@ impl WastTest {
                 "misc_testsuite/simd/canonicalize-nan.wast",
                 "misc_testsuite/simd/issue6725-no-egraph-panic.wast",
                 "misc_testsuite/simd/issue_3327_bnot_lowering.wast",
-                "misc_testsuite/simd/replace-lane-preserve.wast",
                 "misc_testsuite/simd/v128-select.wast",
                 "spec_testsuite/proposals/annotations/simd_lane.wast",
                 "spec_testsuite/proposals/relaxed-simd/i16x8_relaxed_q15mulr_s.wast",
@@ -454,10 +453,6 @@ impl WastTest {
                 "spec_testsuite/simd_i8x16_sat_arith.wast",
                 "spec_testsuite/simd_lane.wast",
                 "spec_testsuite/simd_load.wast",
-                "spec_testsuite/simd_load16_lane.wast",
-                "spec_testsuite/simd_load32_lane.wast",
-                "spec_testsuite/simd_load64_lane.wast",
-                "spec_testsuite/simd_load8_lane.wast",
                 "spec_testsuite/simd_load_zero.wast",
                 "spec_testsuite/simd_splat.wast",
             ];

diff --git a/pulley/src/interp.rs b/pulley/src/interp.rs
@@ -3333,4 +3333,88 @@ impl ExtendedOpVisitor for Interpreter<'_> {
         self.state[dst].set_f64(a);
         ControlFlow::Continue(())
     }
+
+    fn vinsertx8(
+        &mut self,
+        operands: BinaryOperands<VReg, VReg, XReg>,
+        lane: u8,
+    ) -> ControlFlow<Done> {
+        let mut a = self.state[operands.src1].get_u8x16();
+        let b = self.state[operands.src2].get_u32() as u8;
+        unsafe {
+            *a.get_unchecked_mut(usize::from(lane)) = b;
+        }
+        self.state[operands.dst].set_u8x16(a);
+        ControlFlow::Continue(())
+    }
+
+    fn vinsertx16(
+        &mut self,
+        operands: BinaryOperands<VReg, VReg, XReg>,
+        lane: u8,
+    ) -> ControlFlow<Done> {
+        let mut a = self.state[operands.src1].get_u16x8();
+        let b = self.state[operands.src2].get_u32() as u16;
+        unsafe {
+            *a.get_unchecked_mut(usize::from(lane)) = b;
+        }
+        self.state[operands.dst].set_u16x8(a);
+        ControlFlow::Continue(())
+    }
+
+    fn vinsertx32(
+        &mut self,
+        operands: BinaryOperands<VReg, VReg, XReg>,
+        lane: u8,
+    ) -> ControlFlow<Done> {
+        let mut a = self.state[operands.src1].get_u32x4();
+        let b = self.state[operands.src2].get_u32();
+        unsafe {
+            *a.get_unchecked_mut(usize::from(lane)) = b;
+        }
+        self.state[operands.dst].set_u32x4(a);
+        ControlFlow::Continue(())
+    }
+
+    fn vinsertx64(
+        &mut self,
+        operands: BinaryOperands<VReg, VReg, XReg>,
+        lane: u8,
+    ) -> ControlFlow<Done> {
+        let mut a = self.state[operands.src1].get_u64x2();
+        let b = self.state[operands.src2].get_u64();
+        unsafe {
+            *a.get_unchecked_mut(usize::from(lane)) = b;
+        }
+        self.state[operands.dst].set_u64x2(a);
+        ControlFlow::Continue(())
+    }
+
+    fn vinsertf32(
+        &mut self,
+        operands: BinaryOperands<VReg, VReg, FReg>,
+        lane: u8,
+    ) -> ControlFlow<Done> {
+        let mut a = self.state[operands.src1].get_f32x4();
+        let b = self.state[operands.src2].get_f32();
+        unsafe {
+            *a.get_unchecked_mut(usize::from(lane)) = b;
+        }
+        self.state[operands.dst].set_f32x4(a);
+        ControlFlow::Continue(())
+    }
+
+    fn vinsertf64(
+        &mut self,
+        operands: BinaryOperands<VReg, VReg, FReg>,
+        lane: u8,
+    ) -> ControlFlow<Done> {
+        let mut a = self.state[operands.src1].get_f64x2();
+        let b = self.state[operands.src2].get_f64();
+        unsafe {
+            *a.get_unchecked_mut(usize::from(lane)) = b;
+        }
+        self.state[operands.dst].set_f64x2(a);
+        ControlFlow::Continue(())
+    }
 }
diff --git a/pulley/src/lib.rs b/pulley/src/lib.rs
@@ -856,6 +856,19 @@ macro_rules! for_each_extended_op {
             fextractv32x4 = FExtractV32x4 { dst: FReg, src: VReg, lane: u8 };
             /// `dst = src[lane]`
             fextractv64x2 = FExtractV64x2 { dst: FReg, src: VReg, lane: u8 };
+
+            /// `dst = src1; dst[lane] = src2`
+            vinsertx8 = VInsertX8 { operands: BinaryOperands<VReg, VReg, XReg>, lane: u8 };
+            /// `dst = src1; dst[lane] = src2`
+            vinsertx16 = VInsertX16 { operands: BinaryOperands<VReg, VReg, XReg>, lane: u8 };
+            /// `dst = src1; dst[lane] = src2`
+            vinsertx32 = VInsertX32 { operands: BinaryOperands<VReg, VReg, XReg>, lane: u8 };
+            /// `dst = src1; dst[lane] = src2`
+            vinsertx64 = VInsertX64 { operands: BinaryOperands<VReg, VReg, XReg>, lane: u8 };
+            /// `dst = src1; dst[lane] = src2`
+            vinsertf32 = VInsertF32 { operands: BinaryOperands<VReg, VReg, FReg>, lane: u8 };
+            /// `dst = src1; dst[lane] = src2`
+            vinsertf64 = VInsertF64 { operands: BinaryOperands<VReg, VReg, FReg>, lane: u8 };
         }
     };
 }