uart: add default source clock for all targets

components/app_trace/port/port_uart.c

@@ -224,7 +224,7 @@ static esp_err_t esp_apptrace_uart_init(esp_apptrace_uart_data_t *hw_data)
             .parity = UART_PARITY_DISABLE,
             .stop_bits = UART_STOP_BITS_1,
             .flow_ctrl = UART_HW_FLOWCTRL_DISABLE,
-            .source_clk = UART_SCLK_APB,
+            .source_clk = UART_SCLK_DEFAULT,
         };
         ESP_LOGI(TAG, "UART baud rate: %i", CONFIG_APPTRACE_UART_BAUDRATE);
         // We won't use a buffer for sending data.

components/driver/test/test_rs485.c

@@ -164,7 +164,7 @@ static void rs485_init(void)
         .stop_bits = UART_STOP_BITS_1,
         .flow_ctrl = UART_HW_FLOWCTRL_DISABLE,
         .rx_flow_ctrl_thresh = 120,
-        .source_clk = UART_SCLK_APB,
+        .source_clk = UART_SCLK_DEFAULT,
     };
     printf("RS485 port initialization...\r\n");
     TEST_ESP_OK(uart_wait_tx_idle_polling(UART_NUM1));

components/driver/test/test_uart.c

@@ -32,8 +32,6 @@
 // Wait timeout for uart driver
 #define PACKET_READ_TICS    (1000 / portTICK_PERIOD_MS)
 
-#define TEST_DEFAULT_CLK UART_SCLK_APB
-
 static void uart_config(uint32_t baud_rate, uart_sclk_t source_clk)
 {
     uart_config_t uart_config = {
@@ -80,7 +78,7 @@ static void test_task2(void *pvParameters)
 
 TEST_CASE("test uart_wait_tx_done is not blocked when ticks_to_wait=0", "[uart]")
 {
-    uart_config(UART_BAUD_11520, TEST_DEFAULT_CLK);
+    uart_config(UART_BAUD_11520, UART_SCLK_DEFAULT);
 
     SemaphoreHandle_t exit_sema = xSemaphoreCreateBinary();
     exit_flag = false;
@@ -112,7 +110,7 @@ TEST_CASE("test uart get baud-rate", "[uart]")
 #endif
     uint32_t baud_rate2 = 0;
     printf("init uart%d, unuse reftick, baud rate : %d\n", (int)UART_NUM1, (int)UART_BAUD_115200);
-    uart_config(UART_BAUD_115200, TEST_DEFAULT_CLK);
+    uart_config(UART_BAUD_115200, UART_SCLK_DEFAULT);
     uart_get_baudrate(UART_NUM1, &baud_rate2);
     printf("get  baud rate when don't use reftick: %d\n", (int)baud_rate2);
     TEST_ASSERT_UINT32_WITHIN(UART_BAUD_115200 * TOLERANCE, UART_BAUD_115200, baud_rate2);
@@ -129,7 +127,7 @@ TEST_CASE("test uart tx data with break", "[uart]")
     char *psend = (char *)malloc(buf_len);
     TEST_ASSERT_NOT_NULL(psend);
     memset(psend, '0', buf_len);
-    uart_config(UART_BAUD_115200, TEST_DEFAULT_CLK);
+    uart_config(UART_BAUD_115200, UART_SCLK_DEFAULT);
     printf("Uart%d send %d bytes with break\n", UART_NUM1, send_len);
     uart_write_bytes_with_break(UART_NUM1, (const char *)psend, send_len, brk_len);
     uart_wait_tx_done(UART_NUM1, (TickType_t)portMAX_DELAY);
@@ -215,7 +213,7 @@ TEST_CASE("uart general API test", "[uart]")
         .parity = UART_PARITY_DISABLE,
         .stop_bits = UART_STOP_BITS_1,
         .flow_ctrl = UART_HW_FLOWCTRL_DISABLE,
-        .source_clk = TEST_DEFAULT_CLK,
+        .source_clk = UART_SCLK_DEFAULT,
     };
     uart_param_config(uart_num, &uart_config);
     uart_word_len_set_get_test(uart_num);
@@ -268,7 +266,7 @@ TEST_CASE("uart read write test", "[uart]")
         .parity = UART_PARITY_DISABLE,
         .stop_bits = UART_STOP_BITS_1,
         .flow_ctrl = UART_HW_FLOWCTRL_CTS_RTS,
-        .source_clk = TEST_DEFAULT_CLK,
+        .source_clk = UART_SCLK_DEFAULT,
         .rx_flow_ctrl_thresh = 120
     };
     TEST_ESP_OK(uart_driver_install(uart_num, BUF_SIZE * 2, 0, 20, NULL, 0));
@@ -337,7 +335,7 @@ TEST_CASE("uart tx with ringbuffer test", "[uart]")
         .stop_bits = UART_STOP_BITS_1,
         .flow_ctrl = UART_HW_FLOWCTRL_CTS_RTS,
         .rx_flow_ctrl_thresh = 120,
-        .source_clk = TEST_DEFAULT_CLK,
+        .source_clk = UART_SCLK_DEFAULT,
     };
     uart_wait_tx_idle_polling(uart_num);
     TEST_ESP_OK(uart_param_config(uart_num, &uart_config));
@@ -373,7 +371,7 @@ TEST_CASE("uart int state restored after flush", "[uart]")
         .parity    = UART_PARITY_DISABLE,
         .stop_bits = UART_STOP_BITS_1,
         .flow_ctrl = UART_HW_FLOWCTRL_DISABLE,
-        .source_clk = UART_SCLK_APB,
+        .source_clk = UART_SCLK_DEFAULT,
     };
 
     const uart_port_t uart_echo = UART_NUM_1;

components/esp_hw_support/test/test_dport.c

@@ -138,7 +138,7 @@ void run_tasks_with_change_freq_cpu(int cpu_freq_mhz)
 
         esp_rom_uart_tx_wait_idle(uart_num);
         rtc_clk_cpu_freq_set_config(&new_config);
-        uart_ll_set_sclk(UART_LL_GET_HW(uart_num), UART_SCLK_APB);
+        uart_ll_set_sclk(UART_LL_GET_HW(uart_num), UART_SCLK_DEFAULT);
         uart_ll_set_baudrate(UART_LL_GET_HW(uart_num), uart_baud);
         /* adjust RTOS ticks */
         _xt_tick_divisor = cpu_freq_mhz * 1000000 / XT_TICK_PER_SEC;
@@ -151,7 +151,7 @@ void run_tasks_with_change_freq_cpu(int cpu_freq_mhz)
     // return old freq.
     esp_rom_uart_tx_wait_idle(uart_num);
     rtc_clk_cpu_freq_set_config(&old_config);
-    uart_ll_set_sclk(UART_LL_GET_HW(uart_num), UART_SCLK_APB);
+    uart_ll_set_sclk(UART_LL_GET_HW(uart_num), UART_SCLK_DEFAULT);
     uart_ll_set_baudrate(UART_LL_GET_HW(uart_num), uart_baud);
     _xt_tick_divisor = old_config.freq_mhz * 1000000 / XT_TICK_PER_SEC;
 }

components/esp_pm/pm_impl.c

@@ -721,12 +721,14 @@ void esp_pm_impl_init(void)
 {
 #if defined(CONFIG_ESP_CONSOLE_UART)
     //This clock source should be a source which won't be affected by DFS
-    uint32_t clk_source;
-#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
+    uart_sclk_t clk_source = UART_SCLK_DEFAULT;
+#if SOC_UART_SUPPORT_REF_TICK
     clk_source = UART_SCLK_REF_TICK;
-#else
+#elif SOC_UART_SUPPORT_XTAL_CLK
     clk_source = UART_SCLK_XTAL;
-#endif
+#else
+    #error "No UART clock source is aware of DFS"
+#endif // SOC_UART_SUPPORT_xxx
     while(!uart_ll_is_tx_idle(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM)));
     /* When DFS is enabled, override system setting and use REFTICK as UART clock source */
     uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), clk_source);

components/esp_system/test/test_sleep.c

@@ -191,10 +191,11 @@ TEST_CASE("light sleep duration is correct", "[deepsleep][ignore]")
 TEST_CASE("light sleep and frequency switching", "[deepsleep]")
 {
 #ifndef CONFIG_PM_ENABLE
-#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
-    uart_sclk_t clk_source = UART_SCLK_REF_TICK;
-#else
-    uart_sclk_t clk_source = UART_SCLK_XTAL;
+    uart_sclk_t clk_source = UART_SCLK_DEFAULT;
+#if SOC_UART_SUPPORT_REF_TICK
+    clk_source = UART_SCLK_REF_TICK;
+#elif SOC_UART_SUPPORT_XTAL_CLK
+    clk_source = UART_SCLK_XTAL;
 #endif
     uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), clk_source);
     uart_ll_set_baudrate(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), CONFIG_ESP_CONSOLE_UART_BAUDRATE);

components/hal/esp32c2/include/hal/uart_ll.h

@@ -105,7 +105,7 @@ static inline void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
 {
     switch (source_clk) {
         default:
-        case UART_SCLK_APB:
+        case UART_SCLK_PLL_F40M:
             hw->clk_conf.sclk_sel = 1;
             break;
         case UART_SCLK_RTC:
@@ -130,7 +130,7 @@ static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk)
     switch (hw->clk_conf.sclk_sel) {
         default:
         case 1:
-            *source_clk = UART_SCLK_APB;
+            *source_clk = UART_SCLK_PLL_F40M;
             break;
         case 2:
             *source_clk = UART_SCLK_RTC;

components/hal/esp32h2/include/hal/uart_ll.h

@@ -108,7 +108,7 @@ static inline void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
 {
     switch (source_clk) {
         default:
-        case UART_SCLK_APB:
+        case UART_SCLK_AHB:
             hw->clk_conf.sclk_sel = 1;
             break;
         case UART_SCLK_RTC:
@@ -133,7 +133,7 @@ static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk)
     switch (hw->clk_conf.sclk_sel) {
         default:
         case 1:
-            *source_clk = UART_SCLK_APB;
+            *source_clk = UART_SCLK_AHB;
             break;
         case 2:
             *source_clk = UART_SCLK_RTC;

components/hal/include/hal/uart_types.h

@@ -1,16 +1,8 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #pragma once
 
@@ -21,7 +13,7 @@ extern "C" {
 #include <stdint.h>
 #include <stdbool.h>
 #include "soc/soc_caps.h"
-
+#include "soc/clk_tree_defs.h"
 
 /**
  * @brief UART port number, can be UART_NUM_0 ~ (UART_NUM_MAX -1).
@@ -98,18 +90,7 @@ typedef enum {
 /**
  * @brief UART source clock
  */
-typedef enum {
-    UART_SCLK_APB = 0x0,            /*!< UART source clock from APB*/
-#if SOC_UART_SUPPORT_RTC_CLK
-    UART_SCLK_RTC = 0x1,            /*!< UART source clock from RTC*/
-#endif
-#if SOC_UART_SUPPORT_XTAL_CLK
-    UART_SCLK_XTAL = 0x2,           /*!< UART source clock from XTAL*/
-#endif
-#if SOC_UART_SUPPORT_REF_TICK
-    UART_SCLK_REF_TICK = 0x3,       /*!< UART source clock from REF_TICK*/
-#endif
-} uart_sclk_t;
+typedef soc_periph_uart_clk_src_legacy_t uart_sclk_t;
 
 /**
  * @brief UART AT cmd char configuration parameters

components/hal/uart_hal.c

@@ -1,16 +1,8 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 // The HAL layer for UART (common part)
 #include "hal/uart_hal.h"
@@ -138,7 +130,7 @@ void uart_hal_set_loop_back(uart_hal_context_t *hal, bool loop_back_en)
 void uart_hal_init(uart_hal_context_t *hal, int uart_num)
 {
     // Set default clock source
-    uart_ll_set_sclk(hal->dev, UART_SCLK_APB);
+    uart_ll_set_sclk(hal->dev, UART_SCLK_DEFAULT);
     // Set default baud: 115200, use APB clock.
     const uint32_t baud_def = 115200;
     uart_ll_set_baudrate(hal->dev, baud_def);

components/soc/esp32/include/soc/clk_tree_defs.h

@@ -193,6 +193,17 @@ typedef enum {
     TEMPERATURE_SENSOR_SRC_NA,
 } soc_periph_temperature_sensor_clk_src_t;
 
+///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Type of UART clock source, reserved for the legacy UART driver
+ */
+typedef enum {
+    UART_SCLK_APB = SOC_MOD_CLK_APB,          /*!< UART source clock is APB CLK */
+    UART_SCLK_REF_TICK = SOC_MOD_CLK_APB_F1M, /*!< UART source clock is APB_F1M */
+    UART_SCLK_DEFAULT = SOC_MOD_CLK_APB,      /*!< UART source clock default choice is APB */
+} soc_periph_uart_clk_src_legacy_t;
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32c2/include/soc/clk_tree_defs.h

@@ -155,6 +155,18 @@ typedef enum {
     TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,    /*!< Select XTAL as the default choice */
 } soc_periph_temperature_sensor_clk_src_t;
 
+///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Type of UART clock source, reserved for the legacy UART driver
+ */
+typedef enum {
+    UART_SCLK_PLL_F40M = SOC_MOD_CLK_PLL_F40M, /*!< UART source clock is APB CLK */
+    UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST,       /*!< UART source clock is RC_FAST */
+    UART_SCLK_XTAL = SOC_MOD_CLK_XTAL,         /*!< UART source clock is XTAL */
+    UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F40M,  /*!< UART source clock default choice is PLL_F40M */
+} soc_periph_uart_clk_src_legacy_t;
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32c3/include/soc/clk_tree_defs.h

@@ -183,6 +183,18 @@ typedef enum {
     TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,    /*!< Select XTAL as the default choice */
 } soc_periph_temperature_sensor_clk_src_t;
 
+///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Type of UART clock source, reserved for the legacy UART driver
+ */
+typedef enum {
+    UART_SCLK_APB = SOC_MOD_CLK_APB,     /*!< UART source clock is APB CLK */
+    UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */
+    UART_SCLK_XTAL = SOC_MOD_CLK_XTAL,   /*!< UART source clock is XTAL */
+    UART_SCLK_DEFAULT = SOC_MOD_CLK_APB, /*!< UART source clock default choice is APB */
+} soc_periph_uart_clk_src_legacy_t;
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32h2/include/soc/clk_tree_defs.h

@@ -188,6 +188,18 @@ typedef enum {
     TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,    /*!< Select XTAL as the default choice */
 } soc_periph_temperature_sensor_clk_src_t;
 
+///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Type of UART clock source, reserved for the legacy UART driver
+ */
+typedef enum {
+    UART_SCLK_AHB = SOC_MOD_CLK_AHB,     /*!< UART source clock is AHB CLK */
+    UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */
+    UART_SCLK_XTAL = SOC_MOD_CLK_XTAL,   /*!< UART source clock is XTAL */
+    UART_SCLK_DEFAULT = SOC_MOD_CLK_AHB, /*!< UART source clock default choice is AHB */
+} soc_periph_uart_clk_src_legacy_t;
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32s2/include/soc/clk_tree_defs.h

@@ -201,6 +201,17 @@ typedef enum {
     TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_TEMP_SENSOR, /*!< Select RC_FAST as the default choice */
 } soc_periph_temperature_sensor_clk_src_t;
 
+///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Type of UART clock source, reserved for the legacy UART driver
+ */
+typedef enum {
+    UART_SCLK_APB = SOC_MOD_CLK_APB,          /*!< UART source clock is APB CLK */
+    UART_SCLK_REF_TICK = SOC_MOD_CLK_APB_F1M, /*!< UART source clock is APB_F1M */
+    UART_SCLK_DEFAULT = SOC_MOD_CLK_APB,      /*!< UART source clock default choice is APB */
+} soc_periph_uart_clk_src_legacy_t;
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32s3/include/soc/clk_tree_defs.h

@@ -201,6 +201,18 @@ typedef enum {
     TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_TEMP_SENSOR,   /*!< Select RC_FAST as the default choice */
 } soc_periph_temperature_sensor_clk_src_t;
 
+///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Type of UART clock source, reserved for the legacy UART driver
+ */
+typedef enum {
+    UART_SCLK_APB = SOC_MOD_CLK_APB,     /*!< UART source clock is APB CLK */
+    UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */
+    UART_SCLK_XTAL = SOC_MOD_CLK_XTAL,   /*!< UART source clock is XTAL */
+    UART_SCLK_DEFAULT = SOC_MOD_CLK_APB, /*!< UART source clock default choice is APB */
+} soc_periph_uart_clk_src_legacy_t;
+
 #ifdef __cplusplus
 }
 #endif

components/vfs/test/test_vfs_select.c

@@ -95,7 +95,7 @@ static void uart1_init(void)
         .parity    = UART_PARITY_DISABLE,
         .stop_bits = UART_STOP_BITS_1,
         .flow_ctrl = UART_HW_FLOWCTRL_DISABLE,
-        .source_clk = UART_SCLK_APB,
+        .source_clk = UART_SCLK_DEFAULT,
     };
     uart_driver_install(UART_NUM_1, 256, 256, 0, NULL, 0);
     uart_param_config(UART_NUM_1, &uart_config);