Yosys Optimization Issue: Process Stuck at OPT_CLEAN Pass

[PerryLogic]

Version

Yosys 0.30+48

On which OS did this happen?

Linux

Reproduction Steps

Hello,

I encountered an issue while using Yosys to synthesize a Verilog file.

During the synthesis process of my Verilog file rtl.v, the procedure gets stuck at the OPT_CLEAN pass and does not proceed further.

I have minimized the test case as much as possible to help with troubleshooting. Attached is the Verilog file (rtl.v) that triggers this issue. Below is a screenshot of the synthesis log right before the process gets stuck.

design.file.zip

Thank you in advance for your attention to this matter.
I look forward to hearing from you regarding this issue.

Expected Behavior

The synthesis process completes successfully within a reasonable time frame.

Actual Behavior

The synthesis process gets stuck at the OPT_CLEAN pass and does not complete.

[KrystalDelusion]

This is almost certainly the same problem as #4478 given the very large negative offset from peepopt.