Skip to content

Issues: YosysHQ/sby

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

42 Open 94 Closed
42 Open 94 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

Support for Formal Verification Guide in SymbiYosys?
#309 opened Nov 10, 2024 by EPTansuo
1
ERROR: Assert `formal' failed in passes/memory/memory_map.cc:234
#307 opened Oct 31, 2024 by CrazybinaryLi
Not able to identify which assertion failed when using generators
#306 opened Oct 29, 2024 by zputrle
1
Generated test banches cannot be used with Xcelium or Iverilog
#300 opened Oct 11, 2024 by zputrle
Handle inout ports automatically and produce errors if not possible
#299 opened Oct 1, 2024 by jix
1
X/Z bits in property mishandled by btor backend
#295 opened Aug 23, 2024 by nakengelhardt
Pycode
#291 opened Jul 25, 2024 by AdamKeith1
Local sva variables assignment is resulting in error.
#285 opened Jul 22, 2024 by Humblefool14
Previously working example now fails on newest version
#279 opened Jun 2, 2024 by fayalalebrun
3
Error regarding std::bad_alloc
#265 opened Mar 7, 2024 by natureangel
1
Yosys doesn't work on btor pono engine.
#257 opened Dec 20, 2023 by CrazybinaryLi
1
Unexpected behaviour with asynchronous reset
#255 opened Dec 4, 2023 by mpardalos
8
sby depends on click without specifying a version constraint
#234 opened Feb 27, 2023 by whitequark
4
VCD dump for PASS
#233 opened Feb 20, 2023 by marvintau
1
[RFC] Ensuring code is formatted in accordance to pep8
#208 opened Aug 4, 2022 by lethalbit
2
Yices 2 default solver despite being 'optional'
#165 opened May 30, 2022 by KrystalDelusion
3
Absolute paths in Windows discuss to be discussed at next dev jour fixe (see #devel-discuss at https://yosyshq.slack.com/)
#162 opened May 30, 2022 by KrystalDelusion
tests require super_prove, which requires python-pip, which isn't available on ubuntu 20.04
#160 opened May 25, 2022 by programmerjake
5
SV RTL support for local for loops
#118 opened Nov 13, 2020 by lighteningfingers
Support for SVA Local Variables
#114 opened Sep 8, 2020 by dh73
1
Incorrectly instantiated DUT ports in the auto generated testbench when using SystemVerilog interface
#113 opened Sep 4, 2020 by dh73
1
SymbiYosys doesn't handle latches properly
#111 opened Aug 25, 2020 by ZipCPU
1
BMC fails while induction proof succeeds bug
#103 opened Jul 22, 2020 by kentindell
1
vcd file includes blank traces
#91 opened Jun 12, 2020 by mattvenn
7
Generated trace files dump bit vectors for enum signals
#83 opened Apr 12, 2020 by tudortimi
ProTip! Mix and match filters to narrow down what you’re looking for.