Update

YosysHQ-Docs · Jul 26, 2024 · fc03452 · fc03452
1 parent 6b9c970
commit fc03452
Showing 1 changed file with 18 additions and 42 deletions.
diff --git a/source/cmd/synthprop.rst b/source/cmd/synthprop.rst
@@ -17,69 +17,55 @@ synthprop - synthesize SVA properties
 
     ::
 
-        This creates synthesizable properties for selected module.
+        This creates synthesizable properties for the selected module.
 
 
 
     .. code:: yoscrypt
 
         -name <portname>
 
-   
-
     ::
 
-        Name output port for assertions (default: assertions).
+            name of the output port for assertions (default: assertions).
+
 
     .. code:: yoscrypt
 
         -map <filename>
 
-   
-
     ::
 
-        Write port mapping for synthesizable properties.
+            write the port mapping for synthesizable properties into the given file.
+
 
     .. code:: yoscrypt
 
         -or_outputs
 
-   
-
     ::
 
-        Or all outputs together to create a single output that goes high when any ::
-
-        property is violated, instead of generating individual output bits.
-
+            Or all outputs together to create a single output that goes high when
+            any property is violated, instead of generating individual output bits.
 
 
     .. code:: yoscrypt
 
         -reset <portname>
 
-   
-
     ::
 
-        Name of top-level reset input. Latch a high state on the generated outputs ::
-
-        until an asynchronous top-level reset input is activated.
-
+            name of the top-level reset input. Latch a high state on the generated
+            outputs until an asynchronous top-level reset input is activated.
 
 
     .. code:: yoscrypt
 
         -resetn <portname>
 
-   
-
     ::
 
-        Name of top-level reset input (inverse polarity). Latch a high state on the ::
-
-        generated outputs until an asynchronous top-level reset input is activated.
+            like above but with inverse polarity
 
 
 .. raw:: latex
@@ -93,34 +79,24 @@ synthprop - synthesize SVA properties
         
             synthprop [options]
         
-        This creates synthesizable properties for selected module.
+        This creates synthesizable properties for the selected module.
         
         
             -name <portname>
-        
-        Name output port for assertions (default: assertions).
-        
+                name of the output port for assertions (default: assertions).
         
             -map <filename>
-        
-        Write port mapping for synthesizable properties.
-        
+                write the port mapping for synthesizable properties into the given file.
         
             -or_outputs
-        
-        Or all outputs together to create a single output that goes high when any
-        property is violated, instead of generating individual output bits.
-        
+                Or all outputs together to create a single output that goes high when
+                any property is violated, instead of generating individual output bits.
         
             -reset <portname>
-        
-        Name of top-level reset input. Latch a high state on the generated outputs
-        until an asynchronous top-level reset input is activated.
-        
+                name of the top-level reset input. Latch a high state on the generated
+                outputs until an asynchronous top-level reset input is activated.
         
             -resetn <portname>
-        
-        Name of top-level reset input (inverse polarity). Latch a high state on the
-        generated outputs until an asynchronous top-level reset input is activated.
+                like above but with inverse polarity