CPM4 Embedded PCIe Update

Xilinx · Sep 18, 2024 · 98afad2 · 98afad2
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diff --git a/..._PL_PCIe_Root_Port_Driver/Versal_CPM4_PCIe_Root_Port_Design_Linux/debugging.rst b/..._PL_PCIe_Root_Port_Driver/Versal_CPM4_PCIe_Root_Port_Design_Linux/debugging.rst
@@ -3,6 +3,6 @@
 Debugging
 =======================
 
-..    * PS-PCIe Driver Debug Checklist
+..    * <This page is in progress and will be available soon. Please visit later.>
 ..            *   The PCI Express Controller Programing Model section in UG1085 summarizes programming of the PCI Express controller for Endpoint and Root Port mode operations. Review that section to make sure programming of the PS-GT Transceiver Interface, IOU for Reset Pin, PCI Express Controller and Bridge initialization has been done correctly.
 
diff --git a/...t_Port_Driver/Versal_CPM4_PCIe_Root_Port_Design_Linux/device_tree_structure.rst b/...t_Port_Driver/Versal_CPM4_PCIe_Root_Port_Design_Linux/device_tree_structure.rst
@@ -3,6 +3,6 @@
 Device Tree Structure
 =====================
 
-..    * PS-PCIe Driver Debug Checklist
+..    * <This page is in progress and will be available soon. Please visit later.>
 ..            *   The PCI Express Controller Programing Model section in UG1085 summarizes programming of the PCI Express controller for Endpoint and Root Port mode operations. Review that section to make sure programming of the PS-GT Transceiver Interface, IOU for Reset Pin, PCI Express Controller and Bridge initialization has been done correctly.
 
diff --git a/..._Driver/Versal_CPM4_PCIe_Root_Port_Design_Linux/ecam_mapping_and_addressing.rst b/..._Driver/Versal_CPM4_PCIe_Root_Port_Design_Linux/ecam_mapping_and_addressing.rst
@@ -3,6 +3,6 @@
 ECAM Mapping and Addressing
 ===========================
 
-..    * PS-PCIe Driver Debug Checklist
+..    * <This page is in progress and will be available soon. Please visit later.>
 ..            *   The PCI Express Controller Programing Model section in UG1085 summarizes programming of the PCI Express controller for Endpoint and Root Port mode operations. Review that section to make sure programming of the PS-GT Transceiver Interface, IOU for Reset Pin, PCI Express Controller and Bridge initialization has been done correctly.
 
diff --git a/...ort_Driver/Versal_CPM4_PCIe_Root_Port_Design_Linux/hardware_design_creation.rst b/...ort_Driver/Versal_CPM4_PCIe_Root_Port_Design_Linux/hardware_design_creation.rst
@@ -3,6 +3,6 @@
 Hardware Design Creation
 =======================
 
-..    * PS-PCIe Driver Debug Checklist
+..    * <This page is in progress and will be available soon. Please visit later.>
 ..            *   The PCI Express Controller Programing Model section in UG1085 summarizes programming of the PCI Express controller for Endpoint and Root Port mode operations. Review that section to make sure programming of the PS-GT Transceiver Interface, IOU for Reset Pin, PCI Express Controller and Bridge initialization has been done correctly.
 
diff --git a/...t_Driver/Versal_CPM4_PCIe_Root_Port_Design_Linux/petalinux_image_generation.rst b/...t_Driver/Versal_CPM4_PCIe_Root_Port_Design_Linux/petalinux_image_generation.rst
@@ -3,6 +3,6 @@
 Petalinux Image Generation
 ==========================
 
-..    * PS-PCIe Driver Debug Checklist
+..    * <This page is in progress and will be available soon. Please visit later.>
 ..            *   The PCI Express Controller Programing Model section in UG1085 summarizes programming of the PCI Express controller for Endpoint and Root Port mode operations. Review that section to make sure programming of the PS-GT Transceiver Interface, IOU for Reset Pin, PCI Express Controller and Bridge initialization has been done correctly.
 
diff --git a/...ort_Driver/Versal_CPM4_PCIe_Root_Port_Design_Linux/supporting_documentation.rst b/...ort_Driver/Versal_CPM4_PCIe_Root_Port_Design_Linux/supporting_documentation.rst
@@ -3,6 +3,6 @@
 Supporting Documentation
 ========================
 
-..    * PS-PCIe Driver Debug Checklist
+..    * <This page is in progress and will be available soon. Please visit later.>
 ..            *   The PCI Express Controller Programing Model section in UG1085 summarizes programming of the PCI Express controller for Endpoint and Root Port mode operations. Review that section to make sure programming of the PS-GT Transceiver Interface, IOU for Reset Pin, PCI Express Controller and Bridge initialization has been done correctly.
 
diff --git a/...Driver/Versal_CPM4_PCIe_Root_Port_Design_Linux/system_testability_and_setup.rst b/...Driver/Versal_CPM4_PCIe_Root_Port_Design_Linux/system_testability_and_setup.rst
@@ -3,6 +3,6 @@
 System Testability and Setup
 ============================
 
-    * <Under Construction>
+    * <This page is in progress and will be available soon. Please visit later.>
 ..            *   The PCI Express Controller Programing Model section in UG1085 summarizes programming of the PCI Express controller for Endpoint and Root Port mode operations. Review that section to make sure programming of the PS-GT Transceiver Interface, IOU for Reset Pin, PCI Express Controller and Bridge initialization has been done correctly.
 
diff --git a/...t_Driver/Versal_CPM4_PCIe_Root_Port_Design_Linux/tactical_patch_requirement.rst b/...t_Driver/Versal_CPM4_PCIe_Root_Port_Design_Linux/tactical_patch_requirement.rst
@@ -3,6 +3,6 @@
 Tactical Patch Requirement
 ==========================
 
-..    * PS-PCIe Driver Debug Checklist
+..    * <This page is in progress and will be available soon. Please visit later.>
 ..            *   The PCI Express Controller Programing Model section in UG1085 summarizes programming of the PCI Express controller for Endpoint and Root Port mode operations. Review that section to make sure programming of the PS-GT Transceiver Interface, IOU for Reset Pin, PCI Express Controller and Bridge initialization has been done correctly.