Update PIDX_update_mechanism.rst

pciedebug/source/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/qdma_conceptual_topics/PIDX_update_mechanism.rst

@@ -1,8 +1,15 @@
-.. _qdma_conceptual_topics:
+.. _qdma_conceptual_topics_pidx_update_mechanism:
 
 Deciphering the PIDX Update Mechanism in a QDMA Subsystem for CPM5
 ==================================================================
 
-    * This page is in progress and will be available soon. Please visit later.
-..            *   The PCI Express Controller Programing Model section in UG1085 summarizes programming of the PCI Express controller for Endpoint and Root Port mode operations. Review that section to make sure programming of the PS-GT Transceiver Interface, IOU for Reset Pin, PCI Express Controller and Bridge initialization has been done correctly.
+- The blog in the link below aims to provide a conceptual grasp of the PIDX update mechanism, focusing on key aspects such as:
 
+	- Ring Size (Queue Size)
+	- The maximum value of the initial PIDX Update
+    - The Status field in the Queue
+    - The correlation between CIDX value and the number of descriptors that software can purge from the queue
+    - Wrap-around and error scenarios in subsequent PIDX update values
+    - Tracking PIDX updates in the Traffic Manager interface etc.
+
+https://adaptivesupport.amd.com/s/article/Deciphering-PIDX-Update-Mechanism-in-QDMA-Subsystem-for-PCI-Express