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Merge pull request #1251 from jsmonson/feature/fix-non-blocking
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Feature/fix non blocking
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@auphelia
auphelia authored Dec 13, 2024
2 parents d1b286a + 50ed7ef commit ee29287
Showing 1 changed file with 72 additions and 72 deletions.
144 changes: 72 additions & 72 deletions finn-rtllib/fifo/hdl/Q_srl.v
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Original file line number Diff line number Diff line change
Expand Up @@ -184,58 +184,58 @@ module Q_srl (clock, reset, i_d, i_v, i_r, o_d, o_v, o_r, count, maxcount);
end // always @ (posedge clock or negedge reset)

always @* begin // - combi always
srlo_ <= 'bx;
shift_en_o_ <= 1'bx;
shift_en_ <= 1'bx;
addr_ <= 'bx;
state_ <= 2'bx;
srlo_ = 'bx;
shift_en_o_ = 1'bx;
shift_en_ = 1'bx;
addr_ = 'bx;
state_ = 2'bx;
case (state)

state_empty: begin // - (empty, will not produce)
if (i_v) begin // - empty & i_v => consume
srlo_ <= i_d;
shift_en_o_ <= 1;
shift_en_ <= 1'bx;
addr_ <= 0;
state_ <= state_one;
srlo_ = i_d;
shift_en_o_ = 1;
shift_en_ = 1'bx;
addr_ = 0;
state_ = state_one;
end
else begin // - empty & !i_v => idle
srlo_ <= 'bx;
shift_en_o_ <= 0;
shift_en_ <= 1'bx;
addr_ <= 0;
state_ <= state_empty;
srlo_ = 'bx;
shift_en_o_ = 0;
shift_en_ = 1'bx;
addr_ = 0;
state_ = state_empty;
end
end

state_one: begin // - (contains one)
if (i_v && o_b) begin // - one & i_v & o_b => consume
srlo_ <= 'bx;
shift_en_o_ <= 0;
shift_en_ <= 1;
addr_ <= 0;
state_ <= state_more;
srlo_ = 'bx;
shift_en_o_ = 0;
shift_en_ = 1;
addr_ = 0;
state_ = state_more;
end
else if (i_v && !o_b) begin // - one & i_v & !o_b => cons+prod
srlo_ <= i_d;
shift_en_o_ <= 1;
shift_en_ <= 1;
addr_ <= 0;
state_ <= state_one;
srlo_ = i_d;
shift_en_o_ = 1;
shift_en_ = 1;
addr_ = 0;
state_ = state_one;
end
else if (!i_v && o_b) begin // - one & !i_v & o_b => idle
srlo_ <= 'bx;
shift_en_o_ <= 0;
shift_en_ <= 1'bx;
addr_ <= 0;
state_ <= state_one;
srlo_ = 'bx;
shift_en_o_ = 0;
shift_en_ = 1'bx;
addr_ = 0;
state_ = state_one;
end
else if (!i_v && !o_b) begin // - one & !i_v & !o_b => produce
srlo_ <= 'bx;
shift_en_o_ <= 0;
shift_en_ <= 1'bx;
addr_ <= 0;
state_ <= state_empty;
srlo_ = 'bx;
shift_en_o_ = 0;
shift_en_ = 1'bx;
addr_ = 0;
state_ = state_empty;
end
end // case: state_one

Expand All @@ -244,60 +244,60 @@ module Q_srl (clock, reset, i_d, i_v, i_r, o_d, o_v, o_r, count, maxcount);
// - (full, will not consume)
// - (full here if depth==2)
if (o_b) begin // - full & o_b => idle
srlo_ <= 'bx;
shift_en_o_ <= 0;
shift_en_ <= 0;
addr_ <= addr;
state_ <= state_more;
srlo_ = 'bx;
shift_en_o_ = 0;
shift_en_ = 0;
addr_ = addr;
state_ = state_more;
end
else begin // - full & !o_b => produce
srlo_ <= srl[addr];
shift_en_o_ <= 1;
shift_en_ <= 0;
// addr_ <= addr-1;
// state_ <= state_more;
addr_ <= addr_zero_ ? 0 : addr-1;
state_ <= addr_zero_ ? state_one : state_more;
srlo_ = srl[addr];
shift_en_o_ = 1;
shift_en_ = 0;
// addr_ = addr-1;
// state_ = state_more;
addr_ = addr_zero_ ? 0 : addr-1;
state_ = addr_zero_ ? state_one : state_more;
end
end
else begin // - (mid: neither empty nor full)
if (i_v && o_b) begin // - mid & i_v & o_b => consume
srlo_ <= 'bx;
shift_en_o_ <= 0;
shift_en_ <= 1;
addr_ <= addr+1;
state_ <= state_more;
srlo_ = 'bx;
shift_en_o_ = 0;
shift_en_ = 1;
addr_ = addr+1;
state_ = state_more;
end
else if (i_v && !o_b) begin // - mid & i_v & !o_b => cons+prod
srlo_ <= srl[addr];
shift_en_o_ <= 1;
shift_en_ <= 1;
addr_ <= addr;
state_ <= state_more;
srlo_ = srl[addr];
shift_en_o_ = 1;
shift_en_ = 1;
addr_ = addr;
state_ = state_more;
end
else if (!i_v && o_b) begin // - mid & !i_v & o_b => idle
srlo_ <= 'bx;
shift_en_o_ <= 0;
shift_en_ <= 0;
addr_ <= addr;
state_ <= state_more;
srlo_ = 'bx;
shift_en_o_ = 0;
shift_en_ = 0;
addr_ = addr;
state_ = state_more;
end
else if (!i_v && !o_b) begin // - mid & !i_v & !o_b => produce
srlo_ <= srl[addr];
shift_en_o_ <= 1;
shift_en_ <= 0;
addr_ <= addr_zero_ ? 0 : addr-1;
state_ <= addr_zero_ ? state_one : state_more;
srlo_ = srl[addr];
shift_en_o_ = 1;
shift_en_ = 0;
addr_ = addr_zero_ ? 0 : addr-1;
state_ = addr_zero_ ? state_one : state_more;
end
end // else: !if(addr_full)
end // case: state_more

default: begin
srlo_ <= 'bx;
shift_en_o_ <= 1'bx;
shift_en_ <= 1'bx;
addr_ <= 'bx;
state_ <= 2'bx;
srlo_ = 'bx;
shift_en_o_ = 1'bx;
shift_en_ = 1'bx;
addr_ = 'bx;
state_ = 2'bx;
end // case: default

endcase // case(state)
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