Squashed 'data_compression' changes from 05af0e6..2dba8df (#737)

2dba8df Merge pull request #1998 from RepoOps/update_readme_5 08b08e7 update c1dd6b3 update README Co-authored-by: sdausr <[email protected]>
Xilinx · Oct 21, 2022 · 8dfc103 · 8dfc103
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diff --git a/data_compression/README.rst b/data_compression/README.rst
@@ -68,6 +68,27 @@ can enable makefiles in this library to use DEVICE variable as a
 pattern. Otherwise, full path to .xpfm file needs to be provided via
 DEVICE variable.
 
+Source Files and Application Development
+----------------------------------------
+Vitis libraries are organized into L1, L2, and L3 folders, each relating to a different stage of application development.
+
+**L1**: Makefiles and sources in L1 facilitate HLS based flow for quick checks. Tasks at this level include:
+
+* Check the functionality of an individual kernel (C-simulation)
+* Estimate resource usage, latency, etc. (Synthesis)
+* Run cycle accurate simulations (Co-simulation)
+* Package as IP and get final resource utilization/timing details (Export RTL)
+
+	**Note**:  Once RTL (or XO file after packaging IP) is generated, the Vivado flow is invoked for XCLBIN file generation if required.
+
+**L2**: Makefiles and sources in L2 facilitate building XCLBIN file from various sources (HDL, HLS or XO files) of kernels with host code written in OpenCL/XRT framework targeting a device. This flow supports:
+
+* Software emulation to check the functionality
+* Hardware emulation to check RTL level simulation
+* Build and test on hardware
+
+**L3**: Makefiles and sources in L3 demonstrate applications developed involving multiple kernels in pipeline. These Makefiles can be used for executing tasks, as with the L2 Makefiles.
+
 Benchmark Result
 ----------------