[TestNet] Add testSingleClockNetSource()

Signed-off-by: Eddie Hung <[email protected]>
Xilinx · Sep 20, 2024 · f40257b · f40257b
1 parent 29ca463
commit f40257b
Showing 1 changed file with 9 additions and 0 deletions.
diff --git a/test/src/com/xilinx/rapidwright/design/TestNet.java b/test/src/com/xilinx/rapidwright/design/TestNet.java
@@ -354,4 +354,13 @@ public void testInternalConnectNet() {
 
         Assertions.assertEquals("I1", net0.getLogicalNet().getPortInst(f7mux0.getEDIFCellInst(), "I1").getName());
     }
+
+    @Test
+    public void testSingleClockNetSource() {
+        Design design = RapidWrightDCP.loadDCP("bug349.dcp");
+        Net net = design.getNet("CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O");
+        SitePinInst bufg_o = design.getSiteInstFromSiteName("BUFGCTRL_X0Y0").getSitePinInst("O");
+        Assertions.assertSame(bufg_o, net.getSource());
+        Assertions.assertNull(net.getAlternateSource());
+    }
 }