Merge pull request chipsalliance#447 from ucb-bar/axi4-master

Axi4 master

src/main/scala/coreplex/BaseCoreplex.scala

@@ -29,10 +29,10 @@ case object BroadcastConfig extends Field[BroadcastConfig]
 case class BankedL2Config(
   nMemoryChannels:  Int = 1,
   nBanksPerChannel: Int = 1,
-  coherenceManager: (Int, Parameters) => (TLInwardNode, TLOutwardNode) = { case (lineBytes, p) =>
+  coherenceManager: Parameters => (TLInwardNode, TLOutwardNode) = { case p =>
     val BroadcastConfig(nTrackers, bufferless) = p(BroadcastConfig)
-    val bh = LazyModule(new TLBroadcast(lineBytes, nTrackers, bufferless))
-    (bh.node, bh.node)
+    val bh = LazyModule(new TLBroadcast(p(CacheBlockBytes), nTrackers, bufferless))
+    (bh.node, TLWidthWidget(p(L1toL2Config).beatBytes)(bh.node))
   }) {
   val nBanks = nMemoryChannels*nBanksPerChannel
 }
@@ -130,7 +130,7 @@ trait BankedL2CoherenceManagers extends CoreplexNetwork {
     output := bankBar.node
     val mask = ~BigInt((l2Config.nBanksPerChannel-1) * l1tol2_lineBytes)
     for (i <- 0 until l2Config.nBanksPerChannel) {
-      val (in, out) = l2Config.coherenceManager(l1tol2_lineBytes, p)
+      val (in, out) = l2Config.coherenceManager(p)
       in := TLFilter(AddressSet(i * l1tol2_lineBytes, mask))(l1tol2.node)
       bankBar.node := out
     }

src/main/scala/coreplex/Coreplex.scala

@@ -12,32 +12,59 @@ import rocket._
 
 /////
 
+trait L2MasterPort extends CoreplexNetwork
+{
+  val module: L2MasterPortModule
+  val l2in = TLInputNode()
+  l1tol2.node := l2in
+}
+
+trait L2MasterPortBundle extends CoreplexNetworkBundle
+{
+  val outer: L2MasterPort
+  val l2in = outer.l2in.bundleIn
+}
+
+trait L2MasterPortModule extends CoreplexNetworkModule
+{
+  val outer: L2MasterPort
+  val io: L2MasterPortBundle
+}
+
+/////
+
 class DefaultCoreplex(implicit p: Parameters) extends BaseCoreplex
     with CoreplexRISCVPlatform
-    with RocketPlex {
+    with L2MasterPort
+    with RocketTiles {
   override lazy val module = new DefaultCoreplexModule(this, () => new DefaultCoreplexBundle(this))
 }
 
 class DefaultCoreplexBundle[+L <: DefaultCoreplex](_outer: L) extends BaseCoreplexBundle(_outer)
     with CoreplexRISCVPlatformBundle
-    with RocketPlexBundle
+    with L2MasterPortBundle
+    with RocketTilesBundle
 
 class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io)
     with CoreplexRISCVPlatformModule
-    with RocketPlexModule
+    with L2MasterPortModule
+    with RocketTilesModule
 
 /////
 
 class MultiClockCoreplex(implicit p: Parameters) extends BaseCoreplex
     with CoreplexRISCVPlatform
-    with AsyncRocketPlex {
+    with L2MasterPort
+    with AsyncRocketTiles {
   override lazy val module = new MultiClockCoreplexModule(this, () => new MultiClockCoreplexBundle(this))
 }
 
 class MultiClockCoreplexBundle[+L <: MultiClockCoreplex](_outer: L) extends BaseCoreplexBundle(_outer)
     with CoreplexRISCVPlatformBundle
-    with AsyncRocketPlexBundle
+    with L2MasterPortBundle
+    with AsyncRocketTilesBundle
 
 class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io)
     with CoreplexRISCVPlatformModule
-    with AsyncRocketPlexModule
+    with L2MasterPortModule
+    with AsyncRocketTilesModule

src/main/scala/coreplex/RocketPlex.scala → src/main/scala/coreplex/RocketTiles.scala

@@ -8,8 +8,8 @@ import uncore.coherence._
 import rocket._
 import uncore.devices.NTiles
 
-trait RocketPlex extends CoreplexRISCVPlatform {
-  val module: RocketPlexModule
+trait RocketTiles extends CoreplexRISCVPlatform {
+  val module: RocketTilesModule
 
   val rocketTiles = List.tabulate(p(NTiles)) { i => LazyModule(new RocketTile(i)) }
   val tileIntNodes = rocketTiles.map { _ => IntInternalOutputNode() }
@@ -22,13 +22,13 @@ trait RocketPlex extends CoreplexRISCVPlatform {
   }
 }
 
-trait RocketPlexBundle extends CoreplexRISCVPlatformBundle {
-  val outer: CoreplexRISCVPlatform
+trait RocketTilesBundle extends CoreplexRISCVPlatformBundle {
+  val outer: RocketTiles
 }
 
-trait RocketPlexModule extends CoreplexRISCVPlatformModule {
-  val outer: RocketPlex
-  val io: RocketPlexBundle
+trait RocketTilesModule extends CoreplexRISCVPlatformModule {
+  val outer: RocketTiles
+  val io: RocketTilesBundle
 
   outer.rocketTiles.map(_.module).zipWithIndex.foreach { case (tile, i) =>
     tile.io.hartid := UInt(i)
@@ -67,8 +67,8 @@ class AsyncRocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
   }
 }
 
-trait AsyncRocketPlex extends CoreplexRISCVPlatform {
-  val module: AsyncRocketPlexModule
+trait AsyncRocketTiles extends CoreplexRISCVPlatform {
+  val module: AsyncRocketTilesModule
 
   val rocketTiles = List.tabulate(p(NTiles)) { i => LazyModule(new AsyncRocketTile(i)) }
   val tileIntNodes = rocketTiles.map { _ => IntInternalOutputNode() }
@@ -81,18 +81,18 @@ trait AsyncRocketPlex extends CoreplexRISCVPlatform {
   }
 }
 
-trait AsyncRocketPlexBundle extends CoreplexRISCVPlatformBundle {
-  val outer: CoreplexRISCVPlatform
+trait AsyncRocketTilesBundle extends CoreplexRISCVPlatformBundle {
+  val outer: AsyncRocketTiles
 
   val tcrs = Vec(nTiles, new Bundle {
     val clock = Clock(INPUT)
     val reset = Bool(INPUT)
   })
 }
 
-trait AsyncRocketPlexModule extends CoreplexRISCVPlatformModule {
-  val outer: AsyncRocketPlex
-  val io: AsyncRocketPlexBundle
+trait AsyncRocketTilesModule extends CoreplexRISCVPlatformModule {
+  val outer: AsyncRocketTiles
+  val io: AsyncRocketTilesBundle
 
   outer.rocketTiles.map(_.module).zipWithIndex.foreach { case (tile, i) =>
     tile.clock := io.tcrs(i).clock

src/main/scala/groundtest/TestHarness.scala

@@ -12,14 +12,14 @@ class TestHarness(q: Parameters) extends Module {
   }
   implicit val p = q
 
-  val dut = Module(LazyModule(new GroundTestTop(new GroundTestCoreplex()(_))).module)
+  val dut = Module(LazyModule(new GroundTestTop).module)
   io.success := dut.io.success
 
   if (dut.io.mem_axi4.nonEmpty) {
     val memSize = p(ExtMem).size
     require(memSize % dut.io.mem_axi4.size == 0)
-    for (axi <- dut.io.mem_axi4) {
-      Module(LazyModule(new SimAXIMem(memSize / dut.io.mem_axi4.size)).module).io.axi <> axi
+    for (axi4 <- dut.io.mem_axi4) {
+      Module(LazyModule(new SimAXIMem(memSize / dut.io.mem_axi4.size)).module).io.axi4 <> axi4
     }
   }
 }

src/main/scala/groundtest/Top.scala

@@ -6,20 +6,25 @@ import diplomacy._
 import coreplex._
 import rocketchip._
 
-class GroundTestTop[+C <: GroundTestCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends BaseTop(_coreplex)
-    with DirectConnection
+class GroundTestTop(implicit p: Parameters) extends BaseTop
     with PeripheryMasterAXI4Mem
     with PeripheryTestRAM {
   override lazy val module = new GroundTestTopModule(this, () => new GroundTestTopBundle(this))
+
+  val coreplex = LazyModule(new GroundTestCoreplex)
+
+  socBus.node := coreplex.mmio
+  coreplex.mmioInt := intBus.intnode
+  (mem zip coreplex.mem) foreach { case (m, c) => m := c }
 }
 
-class GroundTestTopBundle[+L <: GroundTestTop[GroundTestCoreplex]](_outer: L) extends BaseTopBundle(_outer)
+class GroundTestTopBundle[+L <: GroundTestTop](_outer: L) extends BaseTopBundle(_outer)
     with PeripheryMasterAXI4MemBundle
     with PeripheryTestRAMBundle {
   val success = Bool(OUTPUT)
 }
 
-class GroundTestTopModule[+L <: GroundTestTop[GroundTestCoreplex], +B <: GroundTestTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io)
+class GroundTestTopModule[+L <: GroundTestTop, +B <: GroundTestTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io)
     with PeripheryMasterAXI4MemModule
     with PeripheryTestRAMModule {
   io.success := outer.coreplex.module.io.success

src/main/scala/rocketchip/BaseTop.scala

@@ -11,21 +11,19 @@ import uncore.tilelink2._
 import uncore.devices._
 import util._
 import rocket._
-import coreplex._
 
 /** Enable or disable monitoring of Diplomatic buses */
 case object TLEmitMonitors extends Field[Boolean]
 
-abstract class BareTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit val p: Parameters) extends LazyModule {
-  val coreplex = LazyModule(_coreplex(p))
+abstract class BareTop(implicit val p: Parameters) extends LazyModule {
   TopModule.contents = Some(this)
 }
 
-abstract class BareTopBundle[+L <: BareTop[BaseCoreplex]](_outer: L) extends Bundle {
+abstract class BareTopBundle[+L <: BareTop](_outer: L) extends Bundle {
   val outer = _outer
 }
 
-abstract class BareTopModule[+L <: BareTop[BaseCoreplex], +B <: BareTopBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) {
+abstract class BareTopModule[+L <: BareTop, +B <: BareTopBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) {
   val outer = _outer
   val io = _io ()
 }
@@ -45,8 +43,6 @@ trait TopNetwork extends HasPeripheryParameters {
     TLWidthWidget(socBusConfig.beatBytes)(
     TLAtomicAutomata(arithmetic = peripheryBusArithmetic)(
     socBus.node))
-
-  var coreplexMem = Seq[TLOutwardNode]()
 }
 
 trait TopNetworkBundle extends HasPeripheryParameters {
@@ -61,22 +57,23 @@ trait TopNetworkModule extends HasPeripheryParameters {
 }
 
 /** Base Top with no Periphery */
-class BaseTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends BareTop(_coreplex)
+class BaseTop(implicit p: Parameters) extends BareTop
     with TopNetwork {
   override lazy val module = new BaseTopModule(this, () => new BaseTopBundle(this))
 }
 
-class BaseTopBundle[+L <: BaseTop[BaseCoreplex]](_outer: L) extends BareTopBundle(_outer)
+class BaseTopBundle[+L <: BaseTop](_outer: L) extends BareTopBundle(_outer)
     with TopNetworkBundle
 
-class BaseTopModule[+L <: BaseTop[BaseCoreplex], +B <: BaseTopBundle[L]](_outer: L, _io: () => B) extends BareTopModule(_outer, _io)
+class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle[L]](_outer: L, _io: () => B) extends BareTopModule(_outer, _io)
     with TopNetworkModule
 
-trait DirectConnection extends TopNetwork {
-  val coreplex: BaseCoreplex
+trait L2Crossbar extends TopNetwork {
+  val l2 = LazyModule(new TLXbar)
+}
 
-  socBus.node := coreplex.mmio
-  coreplex.mmioInt := intBus.intnode
+trait L2CrossbarBundle extends TopNetworkBundle {
+}
 
-  coreplexMem = coreplex.mem
+trait L2CrossbarModule extends TopNetworkModule {
 }

src/main/scala/rocketchip/ExampleTop.scala

@@ -5,56 +5,48 @@ package rocketchip
 import Chisel._
 import config._
 import junctions._
-import coreplex._
 import rocketchip._
 
-/** Example Top with Periphery */
-class ExampleTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends BaseTop(_coreplex)
-    with DirectConnection
+/** Example Top with Periphery (w/o coreplex) */
+abstract class ExampleTop(implicit p: Parameters) extends BaseTop
     with PeripheryExtInterrupts
     with PeripheryMasterAXI4Mem
-    with PeripheryMasterAXI4MMIO {
+    with PeripheryMasterAXI4MMIO
+    with PeripherySlaveAXI4 {
   override lazy val module = new ExampleTopModule(this, () => new ExampleTopBundle(this))
 }
 
-class ExampleTopBundle[+L <: ExampleTop[BaseCoreplex]](_outer: L) extends BaseTopBundle(_outer)
+class ExampleTopBundle[+L <: ExampleTop](_outer: L) extends BaseTopBundle(_outer)
     with PeripheryExtInterruptsBundle
     with PeripheryMasterAXI4MemBundle
     with PeripheryMasterAXI4MMIOBundle
+    with PeripherySlaveAXI4Bundle
 
-class ExampleTopModule[+L <: ExampleTop[BaseCoreplex], +B <: ExampleTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io)
+class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io)
     with PeripheryExtInterruptsModule
     with PeripheryMasterAXI4MemModule
     with PeripheryMasterAXI4MMIOModule
+    with PeripherySlaveAXI4Module
 
-class ExampleRocketTop[+C <: DefaultCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends ExampleTop(_coreplex)
+class ExampleRocketTop(implicit p: Parameters) extends ExampleTop
     with PeripheryBootROM
     with PeripheryDTM
     with PeripheryCounter
-    with HardwiredResetVector {
+    with HardwiredResetVector
+    with RocketPlexMaster {
   override lazy val module = new ExampleRocketTopModule(this, () => new ExampleRocketTopBundle(this))
 }
 
-class ExampleRocketTopBundle[+L <: ExampleRocketTop[DefaultCoreplex]](_outer: L) extends ExampleTopBundle(_outer)
+class ExampleRocketTopBundle[+L <: ExampleRocketTop](_outer: L) extends ExampleTopBundle(_outer)
     with PeripheryBootROMBundle
     with PeripheryDTMBundle
     with PeripheryCounterBundle
     with HardwiredResetVectorBundle
+    with RocketPlexMasterBundle
 
-class ExampleRocketTopModule[+L <: ExampleRocketTop[DefaultCoreplex], +B <: ExampleRocketTopBundle[L]](_outer: L, _io: () => B) extends ExampleTopModule(_outer, _io)
+class ExampleRocketTopModule[+L <: ExampleRocketTop, +B <: ExampleRocketTopBundle[L]](_outer: L, _io: () => B) extends ExampleTopModule(_outer, _io)
     with PeripheryBootROMModule
     with PeripheryDTMModule
     with PeripheryCounterModule
     with HardwiredResetVectorModule
-
-/** Example Top with TestRAM */
-class ExampleTopWithTestRAM[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends ExampleTop(_coreplex)
-    with PeripheryTestRAM {
-  override lazy val module = new ExampleTopWithTestRAMModule(this, () => new ExampleTopWithTestRAMBundle(this))
-}
-
-class ExampleTopWithTestRAMBundle[+L <: ExampleTopWithTestRAM[BaseCoreplex]](_outer: L) extends ExampleTopBundle(_outer)
-    with PeripheryTestRAMBundle
-
-class ExampleTopWithTestRAMModule[+L <: ExampleTopWithTestRAM[BaseCoreplex], +B <: ExampleTopWithTestRAMBundle[L]](_outer: L, _io: () => B) extends ExampleTopModule(_outer, _io)
-    with PeripheryTestRAMModule
+    with RocketPlexMasterModule