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Merge pull request chipsalliance#544 from ucb-bar/jchang
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Added access function
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jchang0 authored Feb 2, 2017
2 parents 8225676 + 83a83c7 commit 094b3bc
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Showing 2 changed files with 11 additions and 0 deletions.
2 changes: 2 additions & 0 deletions src/main/scala/diplomacy/Parameters.scala
Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,8 @@ case class IdRange(start: Int, end: Int)

def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start

def range = start until end
}

// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
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9 changes: 9 additions & 0 deletions src/main/scala/uncore/tilelink2/Edges.scala
Original file line number Diff line number Diff line change
Expand Up @@ -158,6 +158,15 @@ class TLEdge(
}
}

def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}

def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) UInt(0) else x(log2Ceil(manager.beatBytes)-1, 0)
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