Pinned Loading

1. ara ara Public

   Forked from pulp-platform/ara

   The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

   C

2. riscv-isa-sim riscv-isa-sim Public

   Forked from riscv-software-src/riscv-isa-sim

   Spike, a RISC-V ISA Simulator

   C

3. riscv-boom riscv-boom Public

   Forked from riscv-boom/riscv-boom

   SonicBOOM: The Berkeley Out-of-Order Machine

   Scala

4. chipyard chipyard Public

   Forked from ucb-bar/chipyard

   An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

   Scala

5. cva6 cva6 Public

   Forked from openhwgroup/cva6

   The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

   Assembly

6. riscv-dv riscv-dv Public

   Forked from chipsalliance/riscv-dv

   Random instruction generator for RISC-V processor verification

   Python