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Fix routing issue #260

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3ee769a
first commit
FriedrichWu Jun 21, 2024
f69f8de
first commit
FriedrichWu Jun 26, 2024
4efc0e6
fix the lef file problem partly, spare_wen0[0] left
FriedrichWu Jul 3, 2024
8ecdc93
temp_fix of gds/lef cell name not unique problem, not elegant
FriedrichWu Jul 10, 2024
fb7f923
fix the [0] problem in spare_wen
FriedrichWu Jul 15, 2024
e6ca825
recrusive placement of dffs-naive edition
FriedrichWu Jul 22, 2024
e3170ab
Simple version without lvs(rutiime problem with magic
FriedrichWu Jul 30, 2024
725c442
fix
FriedrichWu Jul 30, 2024
0ae194f
Simple version fix
FriedrichWu Aug 20, 2024
6743049
clean version
FriedrichWu Sep 5, 2024
20e4549
add io placer
FriedrichWu Sep 5, 2024
ee6be23
first comment
FriedrichWu Sep 17, 2024
61f5ff6
updata io_pin_placer
FriedrichWu Oct 30, 2024
4340636
fix bugs in channel routing, which will add strange shape in m2 at df…
FriedrichWu Oct 31, 2024
1f1f064
fix clk csb overlap problem
FriedrichWu Oct 31, 2024
f56460b
make code clean
FriedrichWu Nov 12, 2024
8658861
first commt
FriedrichWu Nov 17, 2024
4fe635a
add route_outside, remove unused methods
FriedrichWu Nov 20, 2024
bda3adf
more stable
FriedrichWu Dec 15, 2024
474a240
move apporach select to options.py
FriedrichWu Dec 21, 2024
74cab87
add tech fix
FriedrichWu Dec 21, 2024
70ed2a5
deleting spacing, add ci test, fixing merge error
FriedrichWu Dec 22, 2024
691f7a9
speed up constructive approach in 1rw-only
FriedrichWu Dec 23, 2024
48a7065
make channel router better
FriedrichWu Dec 23, 2024
a0ff83c
solve overlap of wmask in channel router
FriedrichWu Dec 23, 2024
2ff7833
Merge pull request #1 from FriedrichWu/dev_supply_fix
FriedrichWu Feb 9, 2025
d4dc7e9
remove gitlab-ci
FriedrichWu Feb 12, 2025
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293 changes: 287 additions & 6 deletions compiler/base/channel_route.py
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102 changes: 81 additions & 21 deletions compiler/base/hierarchy_layout.py
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Original file line number Diff line number Diff line change
Expand Up @@ -1913,6 +1913,42 @@ def add_io_pin(self, instance, pin_name, new_name, start_layer=None, directions=
# Just use the power pin function for now to save code
self.add_power_pin(new_name, pin.center(), start_layer=start_layer, directions=directions)

def add_power_pin_m2(self, name, loc, directions=None, start_layer="m1"):
# same function like normal one, but add power pin at m2
# Hack for min area
if OPTS.tech_name == "sky130":
min_area = drc["minarea_{}".format(self.pwr_grid_layers[1])]
width = round_to_grid(sqrt(min_area))
height = round_to_grid(min_area / width)
else:
width = None
height = None

pin = None
if start_layer == "m2":
pin = self.add_layout_pin_rect_center(text=name,
layer=start_layer,
offset=loc,
width=width,
height=height)
else:
via = self.add_via_stack_center(from_layer=start_layer,
to_layer="m2",
offset=loc,
directions=directions)

if not width:
width = via.width
if not height:
height = via.height
pin = self.add_layout_pin_rect_center(text=name,
layer="m2",
offset=loc,
width=width,
height=height)

return pin

def add_power_pin(self, name, loc, directions=None, start_layer="m1"):
# Hack for min area
if OPTS.tech_name == "sky130":
Expand Down Expand Up @@ -2027,7 +2063,7 @@ def add_perimeter_pin(self, name, pin, side, bbox):
layer=layer,
offset=peri_pin_loc)

def add_dnwell(self, bbox=None, inflate=1):
def add_dnwell(self, bbox=None, inflate=1, route_option="classic"):
""" Create a dnwell, along with nwell moat at border. """

if "dnwell" not in tech_layer:
Expand All @@ -2049,11 +2085,20 @@ def add_dnwell(self, bbox=None, inflate=1):
ul = vector(ll.x, ur.y)
lr = vector(ur.x, ll.y)

# Add the dnwell
self.add_rect("dnwell",
offset=ll,
height=ur.y - ll.y,
width=ur.x - ll.x)
# Hack for sky130 klayout drc rule nwell.6
if OPTS.tech_name == "sky130":
# Apply the drc rule
# Add the dnwell
self.add_rect("dnwell",
offset=ll - vector(0.5 * self.nwell_width, 0.5 * self.nwell_width) - vector(drc["minclosure_nwell_by_dnwell"], drc["minclosure_nwell_by_dnwell"]),
height=ur.y - ll.y + self.nwell_width + 2 * drc["minclosure_nwell_by_dnwell"],
width=ur.x - ll.x + self.nwell_width + 2 * drc["minclosure_nwell_by_dnwell"])
else: # other tech
# Add the dnwell
self.add_rect("dnwell",
offset=ll,
height=ur.y - ll.y,
width=ur.x - ll.x)

# Add the moat
self.add_path("nwell", [ll, lr, ur, ul, ll - vector(0, 0.5 * self.nwell_width)])
Expand All @@ -2063,9 +2108,9 @@ def add_dnwell(self, bbox=None, inflate=1):
tap_spacing = 2
nwell_offset = vector(self.nwell_width, self.nwell_width)

# Every nth tap is connected to gnd
# Every nth tap is connected to vdd
period = 5

moat_pins = []
# BOTTOM
count = 0
loc = ll + nwell_offset.scale(tap_spacing, 0)
Expand All @@ -2080,9 +2125,10 @@ def add_dnwell(self, bbox=None, inflate=1):
to_layer="m1",
offset=loc)
else:
self.add_power_pin(name="vdd",
loc=loc,
start_layer="li")
pin = self.add_power_pin(name="vdd",
loc=loc,
start_layer="li")
moat_pins.append(pin)
count += 1
loc += nwell_offset.scale(tap_spacing, 0)

Expand All @@ -2100,9 +2146,10 @@ def add_dnwell(self, bbox=None, inflate=1):
to_layer="m1",
offset=loc)
else:
self.add_power_pin(name="vdd",
loc=loc,
start_layer="li")
pin = self.add_power_pin(name="vdd",
loc=loc,
start_layer="li")
moat_pins.append(pin)
count += 1
loc += nwell_offset.scale(tap_spacing, 0)

Expand All @@ -2120,9 +2167,15 @@ def add_dnwell(self, bbox=None, inflate=1):
to_layer="m2",
offset=loc)
else:
self.add_power_pin(name="vdd",
loc=loc,
start_layer="li")
if route_option == "classic":
pin = self.add_power_pin(name="vdd",
loc=loc,
start_layer="li")
elif route_option == "quality":
pin = self.add_power_pin_m2(name="vdd",
loc=loc,
start_layer="li")
moat_pins.append(pin)
count += 1
loc += nwell_offset.scale(0, tap_spacing)

Expand All @@ -2140,14 +2193,21 @@ def add_dnwell(self, bbox=None, inflate=1):
to_layer="m2",
offset=loc)
else:
self.add_power_pin(name="vdd",
loc=loc,
start_layer="li")
if route_option == "classic":
pin = self.add_power_pin(name="vdd",
loc=loc,
start_layer="li")
elif route_option == "quality":
pin = self.add_power_pin_m2(name="vdd",
loc=loc,
start_layer="li")
moat_pins.append(pin)
count += 1
loc += nwell_offset.scale(0, tap_spacing)

# Add the gnd ring
# Add the vdd ring
self.add_ring([ll, ur])
return moat_pins

def add_ring(self, bbox=None, width_mult=8, offset=0):
"""
Expand Down
3 changes: 3 additions & 0 deletions compiler/gdsMill/gdsMill/vlsiLayout.py
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Original file line number Diff line number Diff line change
Expand Up @@ -742,6 +742,9 @@ def getAllPinShapes(self, pin_name):
Search for a pin label and return ALL the enclosing rectangles on the same layer
as the pin label.
"""
#debug
for pin in self.pins:
print(pin)
shape_list = []
pin_map = self.pins[pin_name]
for pin_list in pin_map:
Expand Down
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