feat: Vfio automask #868
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feat: Vfio automask #868
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Signed-off-by: Pascal Bauer <[email protected]>
Signed-off-by: Pascal Bauer <[email protected]>
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~/p/villas-node (vfio-automask) [255]> sudo build/fpga/src/villas-fpga-ctrl -c etc/fpga/vc707.json --connect "dma<->3"
09:51:50 dbg kernel Kernel module vfio already loaded...
09:51:50 dbg kernel:vfio:container VFIO extension 1 is available (Type 1)
09:51:50 dbg kernel:vfio:container VFIO extension 2 is not available (SPAPR TCE)
09:51:50 dbg kernel:vfio:container VFIO extension 3 is available (Type 1 v2)
09:51:50 dbg kernel:vfio:container VFIO extension 4 is not available (DMA CC)
09:51:50 dbg kernel:vfio:container VFIO extension 5 is not available (EEH)
09:51:50 dbg kernel:vfio:container VFIO extension 6 is available (Type 1 Nesting)
09:51:50 dbg kernel:vfio:container VFIO extension 7 is not available (SPAPR TCE v2)
09:51:50 dbg kernel:vfio:container VFIO extension 8 is not available (No IOMMU)
09:51:50 dbg kernel:vfio:container VFIO extension 9 is available (Unmap all)
09:51:50 dbg kernel:vfio:container VFIO extension 10 is not available (Update vaddr)
09:51:50 dbg kernel:vfio:container Using VFIO type 1 (Type 1)
09:51:50 dbg kernel:vfio:container Version: 0x0
09:51:50 dbg kernel:vfio:container IOMMU: yes
09:51:50 info streamer Found config for FPGA card vc707
09:51:50 dbg kernel Kernel module vfio_pci already loaded...
09:51:50 dbg kernel Kernel module vfio_iommu_type1 already loaded...
09:51:50 info vc707 Initializing FPGA card vc707
09:51:50 dbg kernel Kernel module vfio_pci already loaded...
09:51:50 info kernel:vfio:container Attach to device 0000:89:00.0 with index 13
09:51:50 dbg kernel:vfio:group path: /dev/vfio/13
09:51:50 dbg kernel:vfio:group VFIO group 13 (fd 4) has path /dev/vfio/13
09:51:50 dbg kernel:vfio:group VFIO group is 13 viable
09:51:50 dbg kernel:vfio:container Attached new group 13 to VFIO container with fd 3
09:51:50 dbg kernel:vfio:device device info: flags: 0x3, num_regions: 9, num_irqs: 5
09:51:50 dbg kernel:vfio:device region 0 info: flags: 0x7, cap_offset: 0x0, size: 0x100000, offset: 0x0
09:51:50 dbg kernel:vfio:device region 1 info: flags: 0x0, cap_offset: 0x0, size: 0x0, offset: 0x10000000000
09:51:50 dbg kernel:vfio:device region 2 info: flags: 0x0, cap_offset: 0x0, size: 0x0, offset: 0x20000000000
09:51:50 dbg kernel:vfio:device region 3 info: flags: 0x0, cap_offset: 0x0, size: 0x0, offset: 0x30000000000
09:51:50 dbg kernel:vfio:device region 4 info: flags: 0x0, cap_offset: 0x0, size: 0x0, offset: 0x40000000000
09:51:50 dbg kernel:vfio:device region 5 info: flags: 0x0, cap_offset: 0x0, size: 0x0, offset: 0x50000000000
09:51:50 dbg kernel:vfio:device region 6 info: flags: 0x0, cap_offset: 0x0, size: 0x0, offset: 0x60000000000
09:51:50 dbg kernel:vfio:device region 7 info: flags: 0x3, cap_offset: 0x0, size: 0x1000, offset: 0x70000000000
09:51:50 dbg kernel:vfio:device irq 0 info: flags: 0x7, count: 0
09:51:50 dbg kernel:vfio:device irq 1 info: flags: 0x9, count: 16
09:51:50 dbg kernel:vfio:device irq 2 info: flags: 0x9, count: 0
09:51:50 dbg kernel:vfio:device irq 3 info: flags: 0x9, count: 1
09:51:50 dbg kernel:vfio:device irq 4 info: flags: 0x9, count: 1
09:51:50 dbg kernel:vfio:device Performing hot reset.
09:51:50 dbg kernel:vfio:device Dependent devices for hot-reset:
09:51:50 dbg kernel:vfio:device 0000:89:00.0: iommu_group=13
09:51:50 dbg card:factory searching for FPGA IP cors config at etc/fpga/vc707-xbar-pcie/vc707-xbar-pcie.json
09:51:50 dbg core:factory IP initialization order:
09:51:50 dbg core:factory dma_pcie_pcie_axi_pcie_0
09:51:50 dbg core:factory dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0
09:51:50 dbg core:factory crossbar_axis_interconnect_0_xbar
09:51:50 dbg core:factory dino_axi_iic_0
09:51:50 dbg core:factory aurora_aurora_8b10b_ch0
09:51:50 dbg core:factory aurora_aurora_8b10b_ch1
09:51:50 dbg core:factory aurora_aurora_8b10b_ch2
09:51:50 dbg core:factory aurora_aurora_8b10b_ch3
09:51:50 dbg core:factory axi_gpio_0
09:51:50 dbg core:factory dino_registerif_0
09:51:50 dbg core:factory dma_pcie_axi_dma_0
09:51:50 dbg core:factory dma_pcie_axi_read_cache_0
09:51:50 info core:factory Configuring dma_pcie_pcie_axi_pcie_0 vlnv=xilinx.com:ip:axi_pcie:2.9
09:51:50 dbg core:factory Using pcie for IP xilinx.com:ip:axi_pcie:2.9
09:51:50 dbg pcie Parse memory view of dma_pcie_pcie_axi_pcie_0 vlnv=xilinx.com:ip:axi_pcie:2.9
09:51:50 dbg memory:graph New vertex: 0
09:51:50 dbg memory:graph New vertex: 1
09:51:50 dbg memory:graph New edge 0 = M_AXI (src=0x0, dest=0x0, size=0x80): 0 -> 1
09:51:50 dbg memory:graph New vertex: 2
09:51:50 dbg memory:graph New edge 1 = M_AXI (src=0x1000, dest=0x0, size=0x400): 0 -> 2
09:51:50 dbg memory:graph New vertex: 3
09:51:50 dbg memory:graph New edge 2 = M_AXI (src=0x2000, dest=0x0, size=0x400): 0 -> 3
09:51:50 dbg memory:graph New vertex: 4
09:51:50 dbg memory:graph New edge 3 = M_AXI (src=0x3000, dest=0x0, size=0x400): 0 -> 4
09:51:50 dbg memory:graph New vertex: 5
09:51:50 dbg memory:graph New edge 4 = M_AXI (src=0x4000, dest=0x0, size=0x400): 0 -> 5
09:51:50 dbg memory:graph New vertex: 6
09:51:50 dbg memory:graph New edge 5 = M_AXI (src=0x5000, dest=0x0, size=0x400): 0 -> 6
09:51:50 dbg memory:graph New vertex: 7
09:51:50 dbg memory:graph New edge 6 = M_AXI (src=0x6000, dest=0x0, size=0x400): 0 -> 7
09:51:50 info core:factory Configuring dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0 vlnv=xilinx.com:module_ref:axi_pcie_intc:1.0
09:51:50 dbg core:factory Using intc for IP xilinx.com:module_ref:axi_pcie_intc:1.0
09:51:50 info core:factory Configuring crossbar_axis_interconnect_0_xbar vlnv=xilinx.com:ip:axis_switch:1.1
09:51:50 dbg core:factory Using switch for IP xilinx.com:ip:axis_switch:1.1
09:51:50 info core:factory Configuring dino_axi_iic_0 vlnv=xilinx.com:ip:axi_iic:2.1
09:51:50 dbg core:factory Using i2c for IP xilinx.com:ip:axi_iic:2.1
09:51:50 dbg i2c Parse IRQs of dino_axi_iic_0 vlnv=xilinx.com:ip:axi_iic:2.1
09:51:50 dbg i2c IRQ: iic2intc_irpt -> dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0:2
09:51:50 info core:factory Configuring aurora_aurora_8b10b_ch0 vlnv=xilinx.com:ip:aurora_8b10b:11.1
09:51:50 dbg core:factory Using aurora_xilinx for IP xilinx.com:ip:aurora_8b10b:11.1
09:51:50 info core:factory Configuring aurora_aurora_8b10b_ch1 vlnv=xilinx.com:ip:aurora_8b10b:11.1
09:51:50 dbg core:factory Using aurora_xilinx for IP xilinx.com:ip:aurora_8b10b:11.1
09:51:50 info core:factory Configuring aurora_aurora_8b10b_ch2 vlnv=xilinx.com:ip:aurora_8b10b:11.1
09:51:50 dbg core:factory Using aurora_xilinx for IP xilinx.com:ip:aurora_8b10b:11.1
09:51:50 info core:factory Configuring aurora_aurora_8b10b_ch3 vlnv=xilinx.com:ip:aurora_8b10b:11.1
09:51:50 dbg core:factory Using aurora_xilinx for IP xilinx.com:ip:aurora_8b10b:11.1
09:51:50 info core:factory Configuring axi_gpio_0 vlnv=xilinx.com:ip:axi_gpio:2.0
09:51:50 dbg core:factory Using gpio for IP xilinx.com:ip:axi_gpio:2.0
09:51:50 info core:factory Configuring dino_registerif_0 vlnv=xilinx.com:module_ref:registerif:1.0
09:51:50 dbg core:factory Using register for IP xilinx.com:module_ref:registerif:1.0
09:51:50 info core:factory Configuring dma_pcie_axi_dma_0 vlnv=xilinx.com:ip:axi_dma:7.1
09:51:50 dbg core:factory Using dma for IP xilinx.com:ip:axi_dma:7.1
09:51:50 dbg dma Parse IRQs of dma_pcie_axi_dma_0 vlnv=xilinx.com:ip:axi_dma:7.1
09:51:50 dbg dma IRQ: mm2s_introut -> dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0:0
09:51:50 dbg dma IRQ: s2mm_introut -> dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0:1
09:51:50 dbg dma Parse memory view of dma_pcie_axi_dma_0 vlnv=xilinx.com:ip:axi_dma:7.1
09:51:50 dbg memory:graph New vertex: 8
09:51:50 dbg memory:graph New vertex: 9
09:51:50 dbg memory:graph New edge 7 = M_AXI_SG (src=0x0, dest=0x0, size=0x100000000): 8 -> 9
09:51:50 dbg memory:graph New vertex: 10
09:51:50 dbg memory:graph New edge 8 = M_AXI_MM2S (src=0x0, dest=0x0, size=0x100000000): 10 -> 9
09:51:50 dbg memory:graph New vertex: 11
09:51:50 dbg memory:graph New edge 9 = M_AXI_S2MM (src=0x0, dest=0x0, size=0x100000000): 11 -> 9
09:51:50 info core:factory Configuring dma_pcie_axi_read_cache_0 vlnv=xilinx.com:module_ref:axi_read_cache:1.0
09:51:50 dbg core:factory Using axis_cache for IP xilinx.com:module_ref:axi_read_cache:1.0
09:51:50 dbg axis_cache Parse memory view of dma_pcie_axi_read_cache_0 vlnv=xilinx.com:module_ref:axi_read_cache:1.0
09:51:50 dbg memory:graph New vertex: 12
09:51:50 dbg memory:graph New edge 10 = M_AXI (src=0x0, dest=0x0, size=0x100000000): 12 -> 9
09:51:50 info core:factory Initializing dma_pcie_pcie_axi_pcie_0 vlnv=xilinx.com:ip:axi_pcie:2.9
09:51:50 dbg kernel:vfio:device Mapping region 0 of size 0x100000 with flags 0x41
09:51:50 dbg memory:graph New vertex: 13
09:51:50 dbg memory:graph New edge 11 = vfio-h2d (src=0x4077f000, dest=0x0, size=0x100000): 13 -> 0
09:51:50 dbg memory:graph New vertex: 14
09:51:50 info dma_pcie_pcie_axi_pcie_0 PCI-BAR0: bus addr=0xd3d00000 size=0x100000
09:51:50 info dma_pcie_pcie_axi_pcie_0 PCI-BAR0: AXI translation offset 0x0
09:51:50 dbg memory:graph New edge 12 = PCI-BAR0 (src=0xd3d00000, dest=0x0, size=0x100000): 14 -> 0
09:51:50 info dma_pcie_pcie_axi_pcie_0 AXI-BAR0: bus addr=0x0 size=0x100000000
09:51:50 info dma_pcie_pcie_axi_pcie_0 AXI-BAR0: PCI translation offset: 0x0
09:51:50 dbg memory:graph New edge 13 = AXI-BAR0 (src=0x0, dest=0x0, size=0x100000000): 9 -> 14
09:51:50 info core:factory Initializing dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0 vlnv=xilinx.com:module_ref:axi_pcie_intc:1.0
09:51:50 err dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0 Failed to change affinity of VFIO-MSI interrupt
09:51:50 dbg kernel:vfio:device Cleaning up device 0000:89:00.0 with fd 5
09:51:50 dbg kernel:vfio:device Unmap region 0 from device 0000:89:00.0
09:51:50 dbg kernel:vfio:device Performing hot reset.
09:51:50 dbg kernel:vfio:device Dependent devices for hot-reset:
09:51:50 dbg kernel:vfio:device 0000:89:00.0: iommu_group=13
09:51:50 dbg kernel:vfio:device Resetting device.
09:51:51 dbg kernel:vfio:group Cleaning up group 13 with fd 4
09:51:51 dbg kernel:vfio:group unsetting group container
09:51:51 dbg kernel:vfio:container Cleaning up container with fd 3
09:51:51 err ctrl Error: Failed to initialize IP dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0 vlnv=xilinx.com:module_ref:axi_pcie_intc:1.0 |
Signed-off-by: Pascal Bauer <[email protected]>
n-eiling
approved these changes
Mar 13, 2025
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rebased on #867.
Add vfio automask support and blueprints for multiple interrupt vectors.