0.9.5

SimEng 0.9.5 is the seventh release of the Simulation Engine. In this release, SimEng is considered to be a beta software therefore there are expected to be bugs and missing features. If you find a bug, such as a missing instruction or missing system call, please submit a PR, or report an issue and we’ll address it as soon as we can.

Please see RELEASE-NOTES.txt for more information about this beta release. Additionally, the documentation for this project can be found at https://uob-hpc.github.io/SimEng/index.html.

What's Changed

• Correcting instantiation of dispatches vector by @jj16791 in #257
• Initial SME Support by @FinnWilkinson in #248
• Initial SST SimEng integration by @rahahahat in #271
• RISC-V Support by @dANW34V3R in #234
• Fix memory leak in Linux::getdents64 by @tom91136 in #267
• Don't const qualify things we'll be moving later. by @tom91136 in #265
• Don't use type punning for RegressionTest::getMemoryValue by @tom91136 in #264
• Fix NUM_GROUPS warning by @dANW34V3R in #278
• AArch64 Instruction support & minor bug fixes by @FinnWilkinson in #273
• Correctly Fill Auxiliary Vector by @dANW34V3R in #300
• Documentation for SST by @rahahahat in #305
• RISC-V Docs by @dANW34V3R in #319
• Various updates to SimEng documentation by @jj16791 in #318
• Fix Incorrect Loop Buffer Behaviour by @dANW34V3R in #306
• In-order Early Halting Fix by @dANW34V3R in #294
• Revert commitMicroOps Function by @dANW34V3R in #321

Full Changelog: 0.9.4...0.9.5