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Full SME(1) instruction support and STREAMING Groups #415

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Full SME(1) instruction support and STREAMING Groups #415

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Commits on Oct 29, 2024

  1. Added STREAMING versions of relevant aarch64 instruction groups.

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    FinnWilkinson committed Oct 29, 2024
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  2. Removed un-used macros from AArch64 Instruction decode.

    @FinnWilkinson
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  3. Moved aarch64 getGroup logic to instruction_decode.

    @FinnWilkinson
    FinnWilkinson committed Oct 29, 2024
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  4. Moved riscv getGroup logic to instruction_decode.

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    FinnWilkinson committed Oct 29, 2024
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  5. Updated unit tests after changing getGroup logic.

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    FinnWilkinson committed Oct 29, 2024
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  6. Added new AArch64 groups to model config and updated integration test.

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  7. Added streaming mode enabled helper functions.

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  8. Added STREAMING group logic to instruction_decode, and logic to chang… 

    …e instruction group to STREAMING if SM mode is different to when instruction was first decoded.
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  9. Fixed minor issues with new streaming groups and updated SME example … 

    …config file.
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  10. Re-wrote checkStreamingGroup function.

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  11. Added unit tests for new AArch64 STREAMING groups functionality.

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  12. Updated aarch64 groups diagram in docs.

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  13. Added SME instruction FMOPS (S and D) support and regression tests.

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  14. Added SME instruction SMOPA (S and D) support and regression tests.

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  15. Added SME instruction SMOPS (S and D) support and regression tests.

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  16. Added SME instructions UMOPA and UMOPS (S and D) support and regressi… 

    …on tests.
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  17. Fix jenkins build error.

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  18. Added SME instructions SUMOPA and SUMOPS (S and D) support and regres… 

    …sion tests.
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  19. Updated SUMOPA and SUMOPS tests.

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  20. Added SME instructions USMOPA and USMOPS (S and D) support and regres… 

    …sion tests.
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  21. Fix jenkins build error pt2.

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  22. Implemented SME STR instruction and regression test.

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  23. Fixed execution logic for vertical ST1D and ST1W SME stores.

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  24. Implemented SME ST1B and ST1H (H and V) instruction logic.

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  25. Implemented SME LD1B and LD1H (H and V) instruction logic.

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  26. Added SME LD1B and LD1H regression tests.

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  27. Updated ST1D and ST1W SME regression tests.

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  28. Added SME ST1B and ST1H regression tests.

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  29. Implemented SME MOVA (Tile to Vec, horizontal) instructions and regre… 

    …ssion test (B, H, S, D)
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  30. Implemented SME MOVA (Tile to Vec, vertical) instructions and regress… 

    …ion test (B, H, S, D)
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  31. Implemented SME MOV (Tile to Vec, vertical and horizontal) instructio… 

    …n alias and regression tests (B, H, S, D)
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  32. Implemented SME MOVA/MOV (Vec to Tile, vertical and horizontal) instr… 

    …uctions and aliases and regression tests (B, H, S, D)
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  33. Implemented SME LDR instruction and regression tests.

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  34. Implemented SME ADDHA and ADDVA (S and D) instructions and regression… 

    … tests.
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  35. Updated ADDHA test to make more specific.

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  36. Corrected ADDVA execution logic.

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  37. Updated ADDVA test to make more specific.

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  38. Added SME MOVA (tile to vec, vec to tile) Quad-word instructions and … 

    …regression tests.
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  39. Implemented SME ST1Q and LD1Q (V and H) instructions and regression t… 

    …ests.
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    FinnWilkinson committed Oct 29, 2024
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  40. Removed werror.

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    FinnWilkinson committed Oct 29, 2024
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  41. NEON instruction logic fixes.

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    FinnWilkinson committed Oct 29, 2024
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  42. Attended PR comments.

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    FinnWilkinson committed Oct 29, 2024
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Commits on Nov 4, 2024

  1. Switched order of concatonation for NEON UMAXP instruction to match H… 

    …ardware.
    @FinnWilkinson
    FinnWilkinson committed Nov 4, 2024
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