Documentation update for 0.9.0 release (#198)

RELEASE-NOTES.txt

@@ -1,6 +1,6 @@
-Welcome to the first ever open source release of the Simulation Engine! SimEng is a fast, easy to use and modify cycle-level simulator for CPUs. Its initial focus is on simulating single Arm cores in server CPUs, and so the instruction set architecture (ISA) target is initially Armv8.4-a+SVE. Later versions of the Arm ISA, and other ISAs such as RISC-V, will be supported in future releases.
+Welcome to the second open source release of the Simulation Engine! SimEng is a fast, easy to use and modify cycle-level simulator for CPUs. Its initial focus is on simulating single Arm cores in server CPUs, and so the instruction set architecture (ISA) target is initially Armv8.4-a+SVE. Later versions of the Arm ISA, and other ISAs such as RISC-V, will be supported in future releases.
 
-This SimEng release should be considered alpha software - you are the first users outside of the core developers, so there *will* be lots of bugs and missing features. The good news is that the code has been designed to be simple to understand and modify, so if you find a bug, such as a missing instruction or missing system call, please submit a PR, or report an issue and we’ll get to it as soon as we can. 
+This SimEng release should be considered beta software - you are the first users outside of the core developers, so there *will* be lots of bugs and missing features. The good news is that the code has been designed to be simple to understand and modify, so if you find a bug, such as a missing instruction or missing system call, please submit a PR, or report an issue and we’ll get to it as soon as we can. 
 
 You can find all the user and developer documentation on the SimEng webpage:
 
@@ -21,10 +21,10 @@ Pre-rolled CPU models in SimEng include:
 Current limitations (to be addressed in a future release):
 * Dynamically linked binaries are not yet supported in SimEng
 * We don't currently support running MPI programs (we’ve had a statically linked OpenMPI single rank program run correctly, but this was painful to build)
-* We only support a subset of Linux's system calls, and these run under emulation. The subset of 42 calls (the answer to life, the universe, and everything) is enough to run all the codes we've tried so far
+* We only support a subset of Linux's system calls, and these run under emulation. The subset of 45 calls is enough to run all the codes we've tried so far
 * C++ binaries haven’t been officially tested yet (they may work, but if not, this should be supported in the next release)
 * No micro-oping support yet, which may impact cycle accuracy in some cases
-* Only partial support for the ISA - we’ve focused on implementing the instructions we’ve seen generated by the compiler for all the test cases we’ve considered, about 550 different instructions so far (~13% of the entire ISA). You’re likely to come across “instruction not implemented” errors, just let us know when you see these
+* Only partial support for the ISA - we’ve focused on implementing the instructions we’ve seen generated by the compiler for all the test cases we’ve considered, about 700 different instructions so far (~16% of the entire ISA). You’re likely to come across “instruction not implemented” errors, just let us know when you see these
 * Single core, single thread only for now
 * SimEng currently only supports a very simple memory model, assuming all load/stores will hit the L1 cache
     * The longer-term plan is to add a full memory model and support for multicore simulations by using the SST framework - http://sst-simulator.org

docs/sphinx/index.rst

@@ -35,7 +35,7 @@ SimEng is a framework for building modern, cycle-accurate processor simulators.
 - Accurate, aiming for simulated cycle times being within 5-10% of real hardware
 - Open source, with a permissive license to enable collaboration across academia and industry
 
-SimEng places an emphasis on performance and ease of use, whilst maintaining a clean, modern, simple and well-documented code base. For example, the current out-of-order (OoO) model is implemented in around 8,000 lines of simple C++, with another 8,000 lines or so implementing the specifics of the Armv8 ISA, and around 11,000 lines of code in the accompanying test suite. SimEng should be simple to read and understand, making it ideal to modify to your requirements and include it in your projects.
+SimEng places an emphasis on performance and ease of use, whilst maintaining a clean, modern, simple and well-documented code base. For example, the current out-of-order (OoO) model is implemented in around 10,000 lines of simple C++, with another 9,000 lines or so implementing the specifics of the Armv8 ISA, and around 13,000 lines of code in the accompanying test suite. SimEng should be simple to read and understand, making it ideal to modify to your requirements and include it in your projects.
 
 
 Features
@@ -67,7 +67,7 @@ For the most recent presentation on SimEng's progress and status, see:
 Release
 -------
 
-This is SimEng's first release, so should be considered alpha level software (version 0.8.0). We expect you to find issues, primarily in unimplemented instructions or unimplemented system calls. Please let us know when you hit these, either by submitting a pull request (PR), or by filing an issue on the Github repo. You can find the all the code and associated test suites for SimEng in the `GitHub repository <https://github.com/UoB-HPC/SimEng>`_. The file `RELEASE_NOTES.txt <https://github.com/UoB-HPC/SimEng/blob/main/RELEASE-NOTES.txt>`_, found in the root of the project, explains the status of the project and includes other relevant information from the SimEng development team.
+This is SimEng's second release, so should be considered beta level software (version 0.9.0). We expect you to find issues, primarily in unimplemented instructions or unimplemented system calls. Please let us know when you hit these, either by submitting a pull request (PR), or by filing an issue on the Github repo. You can find the all the code and associated test suites for SimEng in the `GitHub repository <https://github.com/UoB-HPC/SimEng>`_. The file `RELEASE_NOTES.txt <https://github.com/UoB-HPC/SimEng/blob/main/RELEASE-NOTES.txt>`_, found in the root of the project, explains the status of the project and includes other relevant information from the SimEng development team.
 
 SimEng is released under the same license as LLVM, the permissive `Apache 2.0 <https://www.apache.org/licenses/LICENSE-2.0>`_ license. We are passionate about enabling experimentation with computer architectures, and want users and developers in academic and industry to have complete freedom to use SimEng anyway they wish, including using it in commercial settings.