Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Update project tt_um_wokwi_413386991502909441 (parallellogic-/TinyTapeoutLogic2024A) #418

Merged
merged 1 commit into from
Nov 10, 2024
Merged

Update project tt_um_wokwi_413386991502909441 (parallellogic-/TinyTapeoutLogic2024A) #418

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 2 additions & 2 deletions projects/tt_um_wokwi_413386991502909441/commit_id.json
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
{
"app": "Tiny Tapeout tt09 a48b1c74",
"repo": "https://github.com/parallellogic-/TinyTapeoutLogic2024A",
"commit": "0fcb1fedaf6c05f196e4a815b11fc1bf3cf14554",
"workflow_url": "https://github.com/parallellogic-/TinyTapeoutLogic2024A/actions/runs/11763319531",
"commit": "d6be687f74bebc59ffe3a60895f4014474a9cab5",
"workflow_url": "https://github.com/parallellogic-/TinyTapeoutLogic2024A/actions/runs/11763813925",
"sort_id": 1730503332763,
"openlane_version": "OpenLane2 2.1.9",
"pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"
Expand Down
4 changes: 2 additions & 2 deletions projects/tt_um_wokwi_413386991502909441/info.yaml
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
# Tiny Tapeout project information
project:
title: "Charlieplexing" # Project title
title: "SPI Logic Analyzer with Charlieplexed Display" # Project title
author: "ParallelLogic-" # Your name
discord: "ParallelLogic" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
description: "SPI LED Display Charlieplexer" # One line description of what your project does
description: "Displays contents of register map on charlieplexed display. Generates waveforms for PWM, UART, WS2812 in response to trigger." # One line description of what your project does
language: "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
clock_hz: 10000000 # Clock frequency in Hz (or 0 if not applicable)

Expand Down
182 changes: 91 additions & 91 deletions projects/tt_um_wokwi_413386991502909441/stats/metrics.csv
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,23 +1,23 @@
Metric,Value
design__lint_error__count,0
design__lint_timing_construct__count,0
design__lint_warning__count,11
design__lint_warning__count,0
design__inferred_latch__count,0
design__instance__count,3165
design__instance__area,22758.1
design__instance__count,3142
design__instance__area,23261.1
design__instance_unmapped__count,0
synthesis__check_error__count,0
design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
design__max_fanout_violation__count__corner:nom_tt_025C_1v80,21
design__max_fanout_violation__count__corner:nom_tt_025C_1v80,19
design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
power__internal__total,0.0008356427424587309
power__switching__total,0.00045072208740748465
power__leakage__total,2.5430246353153052E-8
power__total,0.0012863902375102043
clock__skew__worst_hold__corner:nom_tt_025C_1v80,-0.04506906087008847
clock__skew__worst_setup__corner:nom_tt_025C_1v80,-0.04506906087008847
timing__hold__ws__corner:nom_tt_025C_1v80,0.36093956622919066
timing__setup__ws__corner:nom_tt_025C_1v80,4.432120573776598
power__internal__total,0.0008643144392408431
power__switching__total,0.00046338161337189376
power__leakage__total,2.5662092895117894E-8
power__total,0.0013277216348797083
clock__skew__worst_hold__corner:nom_tt_025C_1v80,-0.0842415605561729
clock__skew__worst_setup__corner:nom_tt_025C_1v80,-0.0842415605561729
timing__hold__ws__corner:nom_tt_025C_1v80,0.34978043673732534
timing__setup__ws__corner:nom_tt_025C_1v80,4.120547575333908
timing__hold__tns__corner:nom_tt_025C_1v80,0.0
timing__setup__tns__corner:nom_tt_025C_1v80,0.0
timing__hold__wns__corner:nom_tt_025C_1v80,0
Expand All @@ -28,13 +28,13 @@ timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80,0
timing__setup_vio__count__corner:nom_tt_025C_1v80,0
timing__setup_r2r__ws__corner:nom_tt_025C_1v80,Infinity
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
design__max_slew_violation__count__corner:nom_ss_100C_1v60,50
design__max_fanout_violation__count__corner:nom_ss_100C_1v60,21
design__max_slew_violation__count__corner:nom_ss_100C_1v60,32
design__max_fanout_violation__count__corner:nom_ss_100C_1v60,19
design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
clock__skew__worst_hold__corner:nom_ss_100C_1v60,-0.06953360306572554
clock__skew__worst_setup__corner:nom_ss_100C_1v60,-0.06953360306572554
timing__hold__ws__corner:nom_ss_100C_1v60,0.9468610608025869
timing__setup__ws__corner:nom_ss_100C_1v60,3.2339589699306077
clock__skew__worst_hold__corner:nom_ss_100C_1v60,-0.1328374114971813
clock__skew__worst_setup__corner:nom_ss_100C_1v60,-0.1328374114971813
timing__hold__ws__corner:nom_ss_100C_1v60,0.9207140865878505
timing__setup__ws__corner:nom_ss_100C_1v60,2.84156528572312
timing__hold__tns__corner:nom_ss_100C_1v60,0.0
timing__setup__tns__corner:nom_ss_100C_1v60,0.0
timing__hold__wns__corner:nom_ss_100C_1v60,0
Expand All @@ -46,12 +46,12 @@ timing__setup_vio__count__corner:nom_ss_100C_1v60,0
timing__setup_r2r__ws__corner:nom_ss_100C_1v60,Infinity
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,21
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,19
design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
clock__skew__worst_hold__corner:nom_ff_n40C_1v95,-0.035473097685529094
clock__skew__worst_setup__corner:nom_ff_n40C_1v95,-0.035473097685529094
timing__hold__ws__corner:nom_ff_n40C_1v95,0.13440926529990066
timing__setup__ws__corner:nom_ff_n40C_1v95,4.895203492228827
clock__skew__worst_hold__corner:nom_ff_n40C_1v95,-0.06446354743577887
clock__skew__worst_setup__corner:nom_ff_n40C_1v95,-0.06446354743577887
timing__hold__ws__corner:nom_ff_n40C_1v95,0.12817119950386352
timing__setup__ws__corner:nom_ff_n40C_1v95,4.700645339355775
timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
timing__hold__wns__corner:nom_ff_n40C_1v95,0
Expand All @@ -62,13 +62,13 @@ timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95,0
timing__setup_vio__count__corner:nom_ff_n40C_1v95,0
timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,Infinity
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
design__max_slew_violation__count,76
design__max_fanout_violation__count,21
design__max_slew_violation__count,92
design__max_fanout_violation__count,19
design__max_cap_violation__count,0
clock__skew__worst_hold,-0.03092573507035872
clock__skew__worst_setup,-0.08163470130947478
timing__hold__ws,0.12893647625638113
timing__setup__ws,3.173695174271158
clock__skew__worst_hold,-0.05856237882609233
clock__skew__worst_setup,-0.14337453852190898
timing__hold__ws,0.1260198647770522
timing__setup__ws,2.792765209250956
timing__hold__tns,0.0
timing__setup__tns,0.0
timing__hold__wns,0
Expand All @@ -86,12 +86,12 @@ flow__errors__count,0
design__io,45
design__die__area,75602.5
design__core__area,72564.6
design__instance__count__stdcell,3165
design__instance__area__stdcell,22758.1
design__instance__count__stdcell,3142
design__instance__area__stdcell,23261.1
design__instance__count__macros,0
design__instance__area__macros,0
design__instance__utilization,0.313625
design__instance__utilization__stdcell,0.313625
design__instance__utilization,0.320557
design__instance__utilization__stdcell,0.320557
design__power_grid_violation__count__net:VPWR,0
design__power_grid_violation__count__net:VGND,0
design__power_grid_violation__count,0
Expand All @@ -100,48 +100,48 @@ timing__drv__floating__pins,0
design__instance__displacement__total,0
design__instance__displacement__mean,0
design__instance__displacement__max,0
route__wirelength__estimated,100102
route__wirelength__estimated,96834.4
design__violations,0
design__instance__count__setup_buffer,0
design__instance__count__hold_buffer,3
antenna__violating__nets,6
antenna__violating__pins,10
route__antenna_violation__count,6
route__net,2129
antenna__violating__nets,5
antenna__violating__pins,6
route__antenna_violation__count,5
route__net,2106
route__net__special,2
route__drc_errors__iter:1,3030
route__wirelength__iter:1,124665
route__drc_errors__iter:2,1442
route__wirelength__iter:2,123911
route__drc_errors__iter:3,1382
route__wirelength__iter:3,123618
route__drc_errors__iter:4,373
route__wirelength__iter:4,123539
route__drc_errors__iter:5,46
route__wirelength__iter:5,123524
route__drc_errors__iter:1,2894
route__wirelength__iter:1,118393
route__drc_errors__iter:2,1347
route__wirelength__iter:2,117343
route__drc_errors__iter:3,1266
route__wirelength__iter:3,117335
route__drc_errors__iter:4,282
route__wirelength__iter:4,117326
route__drc_errors__iter:5,3
route__wirelength__iter:5,117276
route__drc_errors__iter:6,0
route__wirelength__iter:6,123514
route__wirelength__iter:6,117284
route__drc_errors,0
route__wirelength,123514
route__vias,21036
route__vias__singlecut,21036
route__wirelength,117284
route__vias,20347
route__vias__singlecut,20347
route__vias__multicut,0
design__disconnected_pin__count,9
design__critical_disconnected_pin__count,0
route__wirelength__max,494.86
route__wirelength__max,504.51
timing__unannotated_net__count__corner:nom_tt_025C_1v80,27
timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
timing__unannotated_net__count__corner:nom_ss_100C_1v60,27
timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0
timing__unannotated_net__count__corner:nom_ff_n40C_1v95,27
timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
design__max_slew_violation__count__corner:min_tt_025C_1v80,0
design__max_fanout_violation__count__corner:min_tt_025C_1v80,21
design__max_fanout_violation__count__corner:min_tt_025C_1v80,19
design__max_cap_violation__count__corner:min_tt_025C_1v80,0
clock__skew__worst_hold__corner:min_tt_025C_1v80,-0.039329984826581496
clock__skew__worst_setup__corner:min_tt_025C_1v80,-0.039329984826581496
timing__hold__ws__corner:min_tt_025C_1v80,0.35704945566318674
timing__setup__ws__corner:min_tt_025C_1v80,4.463006091016752
clock__skew__worst_hold__corner:min_tt_025C_1v80,-0.07657502626510194
clock__skew__worst_setup__corner:min_tt_025C_1v80,-0.07657502626510194
timing__hold__ws__corner:min_tt_025C_1v80,0.34260756312811563
timing__setup__ws__corner:min_tt_025C_1v80,4.147547311877977
timing__hold__tns__corner:min_tt_025C_1v80,0.0
timing__setup__tns__corner:min_tt_025C_1v80,0.0
timing__hold__wns__corner:min_tt_025C_1v80,0
Expand All @@ -154,13 +154,13 @@ timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
timing__unannotated_net__count__corner:min_tt_025C_1v80,27
timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
design__max_slew_violation__count__corner:min_ss_100C_1v60,17
design__max_fanout_violation__count__corner:min_ss_100C_1v60,21
design__max_slew_violation__count__corner:min_ss_100C_1v60,22
design__max_fanout_violation__count__corner:min_ss_100C_1v60,19
design__max_cap_violation__count__corner:min_ss_100C_1v60,0
clock__skew__worst_hold__corner:min_ss_100C_1v60,-0.060608519918345316
clock__skew__worst_setup__corner:min_ss_100C_1v60,-0.060608519918345316
timing__hold__ws__corner:min_ss_100C_1v60,0.9279540731807968
timing__setup__ws__corner:min_ss_100C_1v60,3.288185816700619
clock__skew__worst_hold__corner:min_ss_100C_1v60,-0.1205512390699928
clock__skew__worst_setup__corner:min_ss_100C_1v60,-0.1205512390699928
timing__hold__ws__corner:min_ss_100C_1v60,0.9119674162855733
timing__setup__ws__corner:min_ss_100C_1v60,2.887697274147046
timing__hold__tns__corner:min_ss_100C_1v60,0.0
timing__setup__tns__corner:min_ss_100C_1v60,0.0
timing__hold__wns__corner:min_ss_100C_1v60,0
Expand All @@ -174,12 +174,12 @@ timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
timing__unannotated_net__count__corner:min_ss_100C_1v60,27
timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:min_ff_n40C_1v95,21
design__max_fanout_violation__count__corner:min_ff_n40C_1v95,19
design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
clock__skew__worst_hold__corner:min_ff_n40C_1v95,-0.03092573507035872
clock__skew__worst_setup__corner:min_ff_n40C_1v95,-0.03092573507035872
timing__hold__ws__corner:min_ff_n40C_1v95,0.12893647625638113
timing__setup__ws__corner:min_ff_n40C_1v95,4.916810209255952
clock__skew__worst_hold__corner:min_ff_n40C_1v95,-0.05856237882609233
clock__skew__worst_setup__corner:min_ff_n40C_1v95,-0.05856237882609233
timing__hold__ws__corner:min_ff_n40C_1v95,0.12652140804261125
timing__setup__ws__corner:min_ff_n40C_1v95,4.7212395329558055
timing__hold__tns__corner:min_ff_n40C_1v95,0.0
timing__setup__tns__corner:min_ff_n40C_1v95,0.0
timing__hold__wns__corner:min_ff_n40C_1v95,0
Expand All @@ -193,12 +193,12 @@ timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
timing__unannotated_net__count__corner:min_ff_n40C_1v95,27
timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
design__max_slew_violation__count__corner:max_tt_025C_1v80,0
design__max_fanout_violation__count__corner:max_tt_025C_1v80,21
design__max_fanout_violation__count__corner:max_tt_025C_1v80,19
design__max_cap_violation__count__corner:max_tt_025C_1v80,0
clock__skew__worst_hold__corner:max_tt_025C_1v80,-0.05441963700369005
clock__skew__worst_setup__corner:max_tt_025C_1v80,-0.05441963700369005
timing__hold__ws__corner:max_tt_025C_1v80,0.364503104683265
timing__setup__ws__corner:max_tt_025C_1v80,4.394785992848609
clock__skew__worst_hold__corner:max_tt_025C_1v80,-0.09107298506450229
clock__skew__worst_setup__corner:max_tt_025C_1v80,-0.09107298506450229
timing__hold__ws__corner:max_tt_025C_1v80,0.350802063993479
timing__setup__ws__corner:max_tt_025C_1v80,4.090583099141032
timing__hold__tns__corner:max_tt_025C_1v80,0.0
timing__setup__tns__corner:max_tt_025C_1v80,0.0
timing__hold__wns__corner:max_tt_025C_1v80,0
Expand All @@ -211,13 +211,13 @@ timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
timing__unannotated_net__count__corner:max_tt_025C_1v80,27
timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
design__max_slew_violation__count__corner:max_ss_100C_1v60,76
design__max_fanout_violation__count__corner:max_ss_100C_1v60,21
design__max_slew_violation__count__corner:max_ss_100C_1v60,92
design__max_fanout_violation__count__corner:max_ss_100C_1v60,19
design__max_cap_violation__count__corner:max_ss_100C_1v60,0
clock__skew__worst_hold__corner:max_ss_100C_1v60,-0.08163470130947478
clock__skew__worst_setup__corner:max_ss_100C_1v60,-0.08163470130947478
timing__hold__ws__corner:max_ss_100C_1v60,0.966967200347189
timing__setup__ws__corner:max_ss_100C_1v60,3.173695174271158
clock__skew__worst_hold__corner:max_ss_100C_1v60,-0.14337453852190898
clock__skew__worst_setup__corner:max_ss_100C_1v60,-0.14337453852190898
timing__hold__ws__corner:max_ss_100C_1v60,0.9294619781354891
timing__setup__ws__corner:max_ss_100C_1v60,2.792765209250956
timing__hold__tns__corner:max_ss_100C_1v60,0.0
timing__setup__tns__corner:max_ss_100C_1v60,0.0
timing__hold__wns__corner:max_ss_100C_1v60,0
Expand All @@ -231,12 +231,12 @@ timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
timing__unannotated_net__count__corner:max_ss_100C_1v60,27
timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:max_ff_n40C_1v95,21
design__max_fanout_violation__count__corner:max_ff_n40C_1v95,19
design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
clock__skew__worst_hold__corner:max_ff_n40C_1v95,-0.04319611457457529
clock__skew__worst_setup__corner:max_ff_n40C_1v95,-0.04319611457457529
timing__hold__ws__corner:max_ff_n40C_1v95,0.1378533992642996
timing__setup__ws__corner:max_ff_n40C_1v95,4.867205443112781
clock__skew__worst_hold__corner:max_ff_n40C_1v95,-0.06965145324312252
clock__skew__worst_setup__corner:max_ff_n40C_1v95,-0.06965145324312252
timing__hold__ws__corner:max_ff_n40C_1v95,0.1260198647770522
timing__setup__ws__corner:max_ff_n40C_1v95,4.676738240156568
timing__hold__tns__corner:max_ff_n40C_1v95,0.0
timing__setup__tns__corner:max_ff_n40C_1v95,0.0
timing__hold__wns__corner:max_ff_n40C_1v95,0
Expand All @@ -253,13 +253,13 @@ timing__unannotated_net__count,27
timing__unannotated_net_filtered__count,0
design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79994
design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8
design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000551489
design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000900303
design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000544209
design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000900303
design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000649783
design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000691621
design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000553639
design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000691621
ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
ir__drop__avg,0.0000047500000000000002615095640035036694825976155698299407958984375
ir__drop__worst,0.000055099999999999997612500080013120395960868336260318756103515625
ir__drop__avg,0.0000048500000000000001511052567793047529676186968572437763214111328125
ir__drop__worst,0.000064999999999999994305770190106130712592857889831066131591796875
magic__drc_error__count,0
magic__illegal_overlap__count,0
design__lvs_device_difference__count,0
Expand Down
Loading