Update project tt_um_wokwi_413387064715554817 (raystits/TINYTAPEOUT9)

projects/tt_um_wokwi_413387064715554817/commit_id.json

@@ -1,8 +1,8 @@
 {
-  "app": "Tiny Tapeout tt09 b176ed7c",
+  "app": "Tiny Tapeout tt09 a48b1c74",
   "repo": "https://github.com/raystits/TINYTAPEOUT9",
-  "commit": "533dd09c45feb39b171544ab87ca9401dc1f270a",
-  "workflow_url": "https://github.com/raystits/TINYTAPEOUT9/actions/runs/11637327705",
+  "commit": "7d8d19d5a66ce48ea31945e618fd734f64293439",
+  "workflow_url": "https://github.com/raystits/TINYTAPEOUT9/actions/runs/11715574780",
   "sort_id": 1730502978578,
   "openlane_version": "OpenLane2 2.1.9",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"

projects/tt_um_wokwi_413387064715554817/docs/info.md

@@ -8,21 +8,12 @@ You can also include images in this folder and reference them in the markdown. E
 -->
 
 ## How it works
-
-clock input is anded with in0 to drive out0
-in1 and in2 NAND to out1 and out2
-out3=in3
-out4=in4
-out5=inv in5
-out6=inv in6
-out7=inv in7
+clock input goes into string of d flip flops making the led segments illuminate in a circle.  may want to hit reset to clear the d flip flops if more than 1 segment is illuminated.
 
 ## How to test
-
-flip the dip switches to see if it works
+turn on clock switch or press step button.
 
 ## External hardware
-
-clock (slow)
-dip switch
+clock
+button
 7seg led

projects/tt_um_wokwi_413387064715554817/info.yaml

@@ -1,12 +1,12 @@
 # Tiny Tapeout project information (Wokwi project)
 project:
   wokwi_id:     413387064715554817       # Set this to the ID of your Wokwi project (the number from the project's URL)
-  title:        "RAYS FIRST TAPEOUT"      # Project title
+  title:        "RAYS FIRST TAPEOUT rev 2"      # Project title
   author:       "RAY STITS"      # Your name
   discord:      "raystits"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description:  "rays first tapeout"      # One line description of what your project does
+  description:  "rays first tapeout V3"      # One line description of what your project does
   language:     "Wokwi" # other examples include SystemVerilog, Amaranth, VHDL, etc
-  clock_hz:     60       # Clock frequency in Hz (or 0 if not applicable)
+  clock_hz:     3       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
   tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
@@ -15,14 +15,14 @@ project:
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:
   # Inputs
-  ui[0]: "in0"
-  ui[1]: "in1"
-  ui[2]: "in2"
-  ui[3]: "in3"
-  ui[4]: "in4"
-  ui[5]: "in5"
-  ui[6]: "in6"
-  ui[7]: "in7"
+  ui[0]: ""
+  ui[1]: ""
+  ui[2]: ""
+  ui[3]: ""
+  ui[4]: ""
+  ui[5]: ""
+  ui[6]: ""
+  ui[7]: ""
 
   # Outputs
   uo[0]: "out0"
@@ -31,7 +31,7 @@ pinout:
   uo[3]: "out3"
   uo[4]: "out4"
   uo[5]: "out5"
-  uo[6]: "out6"
+  uo[6]: ""
   uo[7]: "out7"
 
   # Bidirectional pins

projects/tt_um_wokwi_413387064715554817/stats/metrics.csv

@@ -3,21 +3,21 @@ design__lint_error__count,0
 design__lint_timing_construct__count,0
 design__lint_warning__count,0
 design__inferred_latch__count,0
-design__instance__count,254
-design__instance__area,406.64
+design__instance__count,266
+design__instance__area,686.909
 design__instance_unmapped__count,0
 synthesis__check_error__count,0
 design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:nom_tt_025C_1v80,0
 design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
-power__internal__total,0.000002363517523917835
-power__switching__total,0.0000061839209593017586
-power__leakage__total,1.3444574342713622E-9
-power__total,0.000008548782716388814
-clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.0
-clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.0
-timing__hold__ws__corner:nom_tt_025C_1v80,4.1021556201878075
-timing__setup__ws__corner:nom_tt_025C_1v80,5.389751908445677
+power__internal__total,0.00004767047721543349
+power__switching__total,0.000014828061466687359
+power__leakage__total,1.8530227352542283E-9
+power__total,0.00006250039587030187
+clock__skew__worst_hold__corner:nom_tt_025C_1v80,-0.0005484224340996574
+clock__skew__worst_setup__corner:nom_tt_025C_1v80,-0.0005484224340996574
+timing__hold__ws__corner:nom_tt_025C_1v80,0.6430055558892392
+timing__setup__ws__corner:nom_tt_025C_1v80,5.284023146374361
 timing__hold__tns__corner:nom_tt_025C_1v80,0.0
 timing__setup__tns__corner:nom_tt_025C_1v80,0.0
 timing__hold__wns__corner:nom_tt_025C_1v80,0
@@ -31,10 +31,10 @@ timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
 design__max_slew_violation__count__corner:nom_ss_100C_1v60,0
 design__max_fanout_violation__count__corner:nom_ss_100C_1v60,0
 design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
-clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.0
-clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.0
-timing__hold__ws__corner:nom_ss_100C_1v60,4.393323607039214
-timing__setup__ws__corner:nom_ss_100C_1v60,5.00821087665544
+clock__skew__worst_hold__corner:nom_ss_100C_1v60,-0.0007431833137027394
+clock__skew__worst_setup__corner:nom_ss_100C_1v60,-0.0007431833137027394
+timing__hold__ws__corner:nom_ss_100C_1v60,1.5227768366170216
+timing__setup__ws__corner:nom_ss_100C_1v60,4.8900644917471014
 timing__hold__tns__corner:nom_ss_100C_1v60,0.0
 timing__setup__tns__corner:nom_ss_100C_1v60,0.0
 timing__hold__wns__corner:nom_ss_100C_1v60,0
@@ -48,10 +48,10 @@ timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
 design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0
 design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
-clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.0
-clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.0
-timing__hold__ws__corner:nom_ff_n40C_1v95,3.9877107189482546
-timing__setup__ws__corner:nom_ff_n40C_1v95,5.519369117968861
+clock__skew__worst_hold__corner:nom_ff_n40C_1v95,-0.0004547334859593976
+clock__skew__worst_setup__corner:nom_ff_n40C_1v95,-0.0004547334859593976
+timing__hold__ws__corner:nom_ff_n40C_1v95,0.3452960237694315
+timing__setup__ws__corner:nom_ff_n40C_1v95,5.438225135250148
 timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
 timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
 timing__hold__wns__corner:nom_ff_n40C_1v95,0
@@ -65,10 +65,10 @@ timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
 design__max_slew_violation__count,0
 design__max_fanout_violation__count,0
 design__max_cap_violation__count,0
-clock__skew__worst_hold,0.0
-clock__skew__worst_setup,0.0
-timing__hold__ws,3.9844009219736347
-timing__setup__ws,5.005824341174209
+clock__skew__worst_hold,-0.00034749981653563997
+clock__skew__worst_setup,-0.0008924528035852211
+timing__hold__ws,0.34455569928009805
+timing__setup__ws,4.8865224361091615
 timing__hold__tns,0.0
 timing__setup__tns,0.0
 timing__hold__wns,0
@@ -86,12 +86,12 @@ flow__errors__count,0
 design__io,45
 design__die__area,17954.7
 design__core__area,16493.3
-design__instance__count__stdcell,254
-design__instance__area__stdcell,406.64
+design__instance__count__stdcell,266
+design__instance__area__stdcell,686.909
 design__instance__count__macros,0
 design__instance__area__macros,0
-design__instance__utilization,0.0246548
-design__instance__utilization__stdcell,0.0246548
+design__instance__utilization,0.0416477
+design__instance__utilization__stdcell,0.0416477
 design__power_grid_violation__count__net:VGND,0
 design__power_grid_violation__count__net:VPWR,0
 design__power_grid_violation__count,0
@@ -100,40 +100,40 @@ timing__drv__floating__pins,0
 design__instance__displacement__total,0
 design__instance__displacement__mean,0
 design__instance__displacement__max,0
-route__wirelength__estimated,432.431
+route__wirelength__estimated,525.662
 design__violations,0
 design__instance__count__setup_buffer,0
-design__instance__count__hold_buffer,0
+design__instance__count__hold_buffer,6
 antenna__violating__nets,0
 antenna__violating__pins,0
 route__antenna_violation__count,0
-route__net,48
+route__net,59
 route__net__special,2
-route__drc_errors__iter:1,34
-route__wirelength__iter:1,435
+route__drc_errors__iter:1,16
+route__wirelength__iter:1,522
 route__drc_errors__iter:2,0
-route__wirelength__iter:2,392
+route__wirelength__iter:2,497
 route__drc_errors,0
-route__wirelength,392
-route__vias,143
-route__vias__singlecut,143
+route__wirelength,497
+route__vias,188
+route__vias__singlecut,188
 route__vias__multicut,0
-design__disconnected_pin__count,11
+design__disconnected_pin__count,17
 design__critical_disconnected_pin__count,0
-route__wirelength__max,45.78
-timing__unannotated_net__count__corner:nom_tt_025C_1v80,29
+route__wirelength__max,82.67
+timing__unannotated_net__count__corner:nom_tt_025C_1v80,35
 timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
-timing__unannotated_net__count__corner:nom_ss_100C_1v60,29
+timing__unannotated_net__count__corner:nom_ss_100C_1v60,35
 timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0
-timing__unannotated_net__count__corner:nom_ff_n40C_1v95,29
+timing__unannotated_net__count__corner:nom_ff_n40C_1v95,35
 timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
 design__max_slew_violation__count__corner:min_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:min_tt_025C_1v80,0
 design__max_cap_violation__count__corner:min_tt_025C_1v80,0
-clock__skew__worst_hold__corner:min_tt_025C_1v80,0.0
-clock__skew__worst_setup__corner:min_tt_025C_1v80,0.0
-timing__hold__ws__corner:min_tt_025C_1v80,4.0978186448417535
-timing__setup__ws__corner:min_tt_025C_1v80,5.392257459838514
+clock__skew__worst_hold__corner:min_tt_025C_1v80,-0.0004156952677519393
+clock__skew__worst_setup__corner:min_tt_025C_1v80,-0.0004156952677519393
+timing__hold__ws__corner:min_tt_025C_1v80,0.6419490676291264
+timing__setup__ws__corner:min_tt_025C_1v80,5.286238263415741
 timing__hold__tns__corner:min_tt_025C_1v80,0.0
 timing__setup__tns__corner:min_tt_025C_1v80,0.0
 timing__hold__wns__corner:min_tt_025C_1v80,0
@@ -144,15 +144,15 @@ timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
 timing__setup_vio__count__corner:min_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity
 timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
-timing__unannotated_net__count__corner:min_tt_025C_1v80,29
+timing__unannotated_net__count__corner:min_tt_025C_1v80,35
 timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
 design__max_slew_violation__count__corner:min_ss_100C_1v60,0
 design__max_fanout_violation__count__corner:min_ss_100C_1v60,0
 design__max_cap_violation__count__corner:min_ss_100C_1v60,0
-clock__skew__worst_hold__corner:min_ss_100C_1v60,0.0
-clock__skew__worst_setup__corner:min_ss_100C_1v60,0.0
-timing__hold__ws__corner:min_ss_100C_1v60,4.386851894801036
-timing__setup__ws__corner:min_ss_100C_1v60,5.01234268278074
+clock__skew__worst_hold__corner:min_ss_100C_1v60,-0.0005659362028084424
+clock__skew__worst_setup__corner:min_ss_100C_1v60,-0.0005659362028084424
+timing__hold__ws__corner:min_ss_100C_1v60,1.522597424571168
+timing__setup__ws__corner:min_ss_100C_1v60,4.893753096828437
 timing__hold__tns__corner:min_ss_100C_1v60,0.0
 timing__setup__tns__corner:min_ss_100C_1v60,0.0
 timing__hold__wns__corner:min_ss_100C_1v60,0
@@ -163,15 +163,15 @@ timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
 timing__setup_vio__count__corner:min_ss_100C_1v60,0
 timing__setup_r2r__ws__corner:min_ss_100C_1v60,Infinity
 timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
-timing__unannotated_net__count__corner:min_ss_100C_1v60,29
+timing__unannotated_net__count__corner:min_ss_100C_1v60,35
 timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
 design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
 design__max_fanout_violation__count__corner:min_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
-clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.0
-clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.0
-timing__hold__ws__corner:min_ff_n40C_1v95,3.9844009219736347
-timing__setup__ws__corner:min_ff_n40C_1v95,5.5211579093567265
+clock__skew__worst_hold__corner:min_ff_n40C_1v95,-0.00034749981653563997
+clock__skew__worst_setup__corner:min_ff_n40C_1v95,-0.00034749981653563997
+timing__hold__ws__corner:min_ff_n40C_1v95,0.34455569928009805
+timing__setup__ws__corner:min_ff_n40C_1v95,5.4399490896115426
 timing__hold__tns__corner:min_ff_n40C_1v95,0.0
 timing__setup__tns__corner:min_ff_n40C_1v95,0.0
 timing__hold__wns__corner:min_ff_n40C_1v95,0
@@ -182,15 +182,15 @@ timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
 timing__setup_vio__count__corner:min_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:min_ff_n40C_1v95,Infinity
 timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
-timing__unannotated_net__count__corner:min_ff_n40C_1v95,29
+timing__unannotated_net__count__corner:min_ff_n40C_1v95,35
 timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
 design__max_slew_violation__count__corner:max_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:max_tt_025C_1v80,0
 design__max_cap_violation__count__corner:max_tt_025C_1v80,0
-clock__skew__worst_hold__corner:max_tt_025C_1v80,0.0
-clock__skew__worst_setup__corner:max_tt_025C_1v80,0.0
-timing__hold__ws__corner:max_tt_025C_1v80,4.104503075817465
-timing__setup__ws__corner:max_tt_025C_1v80,5.388310394829736
+clock__skew__worst_hold__corner:max_tt_025C_1v80,-0.0006833145354066231
+clock__skew__worst_setup__corner:max_tt_025C_1v80,-0.0006833145354066231
+timing__hold__ws__corner:max_tt_025C_1v80,0.6441818927282499
+timing__setup__ws__corner:max_tt_025C_1v80,5.281634834536241
 timing__hold__tns__corner:max_tt_025C_1v80,0.0
 timing__setup__tns__corner:max_tt_025C_1v80,0.0
 timing__hold__wns__corner:max_tt_025C_1v80,0
@@ -201,15 +201,15 @@ timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
 timing__setup_vio__count__corner:max_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity
 timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
-timing__unannotated_net__count__corner:max_tt_025C_1v80,29
+timing__unannotated_net__count__corner:max_tt_025C_1v80,35
 timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
 design__max_slew_violation__count__corner:max_ss_100C_1v60,0
 design__max_fanout_violation__count__corner:max_ss_100C_1v60,0
 design__max_cap_violation__count__corner:max_ss_100C_1v60,0
-clock__skew__worst_hold__corner:max_ss_100C_1v60,0.0
-clock__skew__worst_setup__corner:max_ss_100C_1v60,0.0
-timing__hold__ws__corner:max_ss_100C_1v60,4.39665116758273
-timing__setup__ws__corner:max_ss_100C_1v60,5.005824341174209
+clock__skew__worst_hold__corner:max_ss_100C_1v60,-0.0008924528035852211
+clock__skew__worst_setup__corner:max_ss_100C_1v60,-0.0008924528035852211
+timing__hold__ws__corner:max_ss_100C_1v60,1.5250022787328226
+timing__setup__ws__corner:max_ss_100C_1v60,4.8865224361091615
 timing__hold__tns__corner:max_ss_100C_1v60,0.0
 timing__setup__tns__corner:max_ss_100C_1v60,0.0
 timing__hold__wns__corner:max_ss_100C_1v60,0
@@ -220,15 +220,15 @@ timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
 timing__setup_vio__count__corner:max_ss_100C_1v60,0
 timing__setup_r2r__ws__corner:max_ss_100C_1v60,Infinity
 timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
-timing__unannotated_net__count__corner:max_ss_100C_1v60,29
+timing__unannotated_net__count__corner:max_ss_100C_1v60,35
 timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
 design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
 design__max_fanout_violation__count__corner:max_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
-clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.0
-clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.0
-timing__hold__ws__corner:max_ff_n40C_1v95,3.9895208266187967
-timing__setup__ws__corner:max_ff_n40C_1v95,5.518365476326214
+clock__skew__worst_hold__corner:max_ff_n40C_1v95,-0.0005807576806063684
+clock__skew__worst_setup__corner:max_ff_n40C_1v95,-0.0005807576806063684
+timing__hold__ws__corner:max_ff_n40C_1v95,0.34612325096847535
+timing__setup__ws__corner:max_ff_n40C_1v95,5.4362169637864115
 timing__hold__tns__corner:max_ff_n40C_1v95,0.0
 timing__setup__tns__corner:max_ff_n40C_1v95,0.0
 timing__hold__wns__corner:max_ff_n40C_1v95,0
@@ -239,19 +239,19 @@ timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:max_ff_n40C_1v95,Infinity
 timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0
-timing__unannotated_net__count__corner:max_ff_n40C_1v95,29
+timing__unannotated_net__count__corner:max_ff_n40C_1v95,35
 timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0
-timing__unannotated_net__count,29
+timing__unannotated_net__count,35
 timing__unannotated_net_filtered__count,0
-design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79999
+design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79996
 design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8
-design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.00000829103
-design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000975236
-design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,1.53998E-7
-design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000975236
+design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000393765
+design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000449734
+design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000103972
+design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000449734
 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
-ir__drop__avg,1.28000000000000007972043706595821621618824792676605284214019775390625E-7
-ir__drop__worst,0.00000829000000000000024954864563664358456662739627063274383544921875
+ir__drop__avg,9.67000000000000016592521627500911307606656919233500957489013671875E-7
+ir__drop__worst,0.0000394000000000000022404821053978452027877210639417171478271484375
 magic__drc_error__count,0
 magic__illegal_overlap__count,0
 design__lvs_device_difference__count,0