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Update project tt_um_rebeccargb_colorbars (RebeccaRGB/tt-colorbars) #122

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merged 1 commit into from
Nov 6, 2024
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Update project tt_um_rebeccargb_colorbars (RebeccaRGB/tt-colorbars) #122

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8 changes: 4 additions & 4 deletions projects/tt_um_rebeccargb_colorbars/commit_id.json
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Open in desktop
Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
{
"app": "Tiny Tapeout tt09 96f3577c",
"app": "Tiny Tapeout tt09 a48b1c74",
"repo": "https://github.com/RebeccaRGB/tt-colorbars",
"commit": "a7fb00abafd37deafd05f827c70b027c75b4371f",
"workflow_url": "https://github.com/RebeccaRGB/tt-colorbars/actions/runs/10873314401",
"commit": "87cceea95d809c363551a3aeb4085f4fecafb1a8",
"workflow_url": "https://github.com/RebeccaRGB/tt-colorbars/actions/runs/11711285607",
"sort_id": 1727070970955,
"openlane_version": "OpenLane2 2.0.8",
"openlane_version": "OpenLane2 2.1.9",
"pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"
}
224 changes: 112 additions & 112 deletions projects/tt_um_rebeccargb_colorbars/stats/metrics.csv
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Original file line number Diff line number Diff line change
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timing__setup_r2r__ws__corner:max_ss_100C_1v60,16.870649
timing__setup_r2r__ws__corner:max_ss_100C_1v60,Infinity
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
timing__unannotated_net__count__corner:max_ss_100C_1v60,17
timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:max_ff_n40C_1v95,2
design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.002243
clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.002243
timing__hold__ws__corner:max_ff_n40C_1v95,0.127467
timing__setup__ws__corner:max_ff_n40C_1v95,8.150444
clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.0012631285264153706
clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.0012631285264153706
timing__hold__ws__corner:max_ff_n40C_1v95,0.1298565736140614
timing__setup__ws__corner:max_ff_n40C_1v95,8.092775567632069
timing__hold__tns__corner:max_ff_n40C_1v95,0.0
timing__setup__tns__corner:max_ff_n40C_1v95,0.0
timing__hold__wns__corner:max_ff_n40C_1v95,0.0
timing__hold__wns__corner:max_ff_n40C_1v95,0
timing__setup__wns__corner:max_ff_n40C_1v95,0.0
timing__hold_vio__count__corner:max_ff_n40C_1v95,0
timing__hold_r2r__ws__corner:max_ff_n40C_1v95,0.127467
timing__hold_r2r__ws__corner:max_ff_n40C_1v95,Infinity
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
timing__setup_vio__count__corner:max_ff_n40C_1v95,0
timing__setup_r2r__ws__corner:max_ff_n40C_1v95,18.818783
timing__setup_r2r__ws__corner:max_ff_n40C_1v95,Infinity
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0
timing__unannotated_net__count__corner:max_ff_n40C_1v95,17
timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0
timing__unannotated_net__count,17
timing__unannotated_net_filtered__count,0
design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79995
design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79994
design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.79999
design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000526095
design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000700303
design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000801221
design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000700303
design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000568003
design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000666869
design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.000007423
design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000666869
ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
ir__drop__avg,0.000007869999999999999188587430920538423606558353640139102935791015625
ir__drop__worst,0.0000525999999999999978315089188551922916303738020360469818115234375
ir__drop__avg,0.0000073499999999999999320964179372328572981132310815155506134033203125
ir__drop__worst,0.00005679999999999999827672569896463983241119422018527984619140625
magic__drc_error__count,0
magic__illegal_overlap__count,0
design__lvs_device_difference__count,0
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