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Update project tt_um_senolgulgonul (senolgulgonul/tt09-senolgulgonul) #115

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merged 1 commit into from
Nov 6, 2024
Merged

Update project tt_um_senolgulgonul (senolgulgonul/tt09-senolgulgonul) #115

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4 changes: 2 additions & 2 deletions projects/tt_um_senolgulgonul/commit_id.json
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
{
"app": "Tiny Tapeout tt09 a48b1c74",
"repo": "https://github.com/senolgulgonul/tt09-senolgulgonul",
"commit": "288ca74f0aea9d18a309147f2a8742d7b9beddf3",
"workflow_url": "https://github.com/senolgulgonul/tt09-senolgulgonul/actions/runs/11704449707",
"commit": "21918c1c05d6a6f434cd4cb54d2dac90440da411",
"workflow_url": "https://github.com/senolgulgonul/tt09-senolgulgonul/actions/runs/11708849893",
"sort_id": 1730725111692,
"openlane_version": "OpenLane2 2.1.9",
"pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"
Expand Down
138 changes: 69 additions & 69 deletions projects/tt_um_senolgulgonul/stats/metrics.csv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3,21 +3,21 @@ design__lint_error__count,0
design__lint_timing_construct__count,0
design__lint_warning__count,0
design__inferred_latch__count,0
design__instance__count,286
design__instance__area,938.4
design__instance__count,289
design__instance__area,942.154
design__instance_unmapped__count,0
synthesis__check_error__count,0
design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
design__max_fanout_violation__count__corner:nom_tt_025C_1v80,0
design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
power__internal__total,0.00005824807158205658
power__switching__total,0.00001219865407620091
power__leakage__total,1.8443998550665697E-9
power__total,0.00007044856465654448
clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.0006913636525628001
clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.0006913636525628001
timing__hold__ws__corner:nom_tt_025C_1v80,0.33877274167030175
timing__setup__ws__corner:nom_tt_025C_1v80,14.7000176192399
power__internal__total,0.00005628330836771056
power__switching__total,0.000011626812010945287
power__leakage__total,1.9286874319845992E-9
power__total,0.00006791204941691831
clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.0012925494374000175
clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.0012925494374000175
timing__hold__ws__corner:nom_tt_025C_1v80,0.33075532138237423
timing__setup__ws__corner:nom_tt_025C_1v80,14.704005540457139
timing__hold__tns__corner:nom_tt_025C_1v80,0.0
timing__setup__tns__corner:nom_tt_025C_1v80,0.0
timing__hold__wns__corner:nom_tt_025C_1v80,0
Expand All @@ -31,10 +31,10 @@ timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
design__max_slew_violation__count__corner:nom_ss_100C_1v60,0
design__max_fanout_violation__count__corner:nom_ss_100C_1v60,0
design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.0009962586593235034
clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.0009962586593235034
timing__hold__ws__corner:nom_ss_100C_1v60,0.9368472929264692
timing__setup__ws__corner:nom_ss_100C_1v60,13.698894850663342
clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.0014997448152305728
clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.0014997448152305728
timing__hold__ws__corner:nom_ss_100C_1v60,0.9373745378557752
timing__setup__ws__corner:nom_ss_100C_1v60,13.705788003573586
timing__hold__tns__corner:nom_ss_100C_1v60,0.0
timing__setup__tns__corner:nom_ss_100C_1v60,0.0
timing__hold__wns__corner:nom_ss_100C_1v60,0
Expand All @@ -48,10 +48,10 @@ timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,0
design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.000582561793072408
clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.000582561793072408
timing__hold__ws__corner:nom_ff_n40C_1v95,0.12164924967240093
timing__setup__ws__corner:nom_ff_n40C_1v95,15.063478002428946
clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.0012136403336930827
clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.0012136403336930827
timing__hold__ws__corner:nom_ff_n40C_1v95,0.11182885489706622
timing__setup__ws__corner:nom_ff_n40C_1v95,15.066204710254542
timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
timing__hold__wns__corner:nom_ff_n40C_1v95,0
Expand All @@ -65,10 +65,10 @@ timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
design__max_slew_violation__count,0
design__max_fanout_violation__count,0
design__max_cap_violation__count,0
clock__skew__worst_hold,0.0012515544510563162
clock__skew__worst_setup,0.00039143689397780595
timing__hold__ws,0.1179136266446428
timing__setup__ws,13.688949916616698
clock__skew__worst_hold,0.002018052448935568
clock__skew__worst_setup,0.0010730583392239918
timing__hold__ws,0.10889101040179083
timing__setup__ws,13.69707941392213
timing__hold__tns,0.0
timing__setup__tns,0.0
timing__hold__wns,0
Expand All @@ -86,12 +86,12 @@ flow__errors__count,0
design__io,45
design__die__area,17954.7
design__core__area,16493.3
design__instance__count__stdcell,286
design__instance__area__stdcell,938.4
design__instance__count__stdcell,289
design__instance__area__stdcell,942.154
design__instance__count__macros,0
design__instance__area__macros,0
design__instance__utilization,0.0568958
design__instance__utilization__stdcell,0.0568958
design__instance__utilization,0.0571234
design__instance__utilization__stdcell,0.0571234
design__power_grid_violation__count__net:VPWR,0
design__power_grid_violation__count__net:VGND,0
design__power_grid_violation__count,0
Expand All @@ -100,31 +100,31 @@ timing__drv__floating__pins,0
design__instance__displacement__total,0
design__instance__displacement__mean,0
design__instance__displacement__max,0
route__wirelength__estimated,1042.37
route__wirelength__estimated,973.064
design__violations,0
design__instance__count__setup_buffer,0
design__instance__count__hold_buffer,1
antenna__violating__nets,0
antenna__violating__pins,0
route__antenna_violation__count,0
route__net,79
route__net,82
route__net__special,2
route__drc_errors__iter:1,95
route__wirelength__iter:1,1197
route__drc_errors__iter:2,18
route__wirelength__iter:2,1185
route__drc_errors__iter:3,8
route__wirelength__iter:3,1150
route__drc_errors__iter:1,29
route__wirelength__iter:1,1073
route__drc_errors__iter:2,6
route__wirelength__iter:2,1047
route__drc_errors__iter:3,13
route__wirelength__iter:3,1028
route__drc_errors__iter:4,0
route__wirelength__iter:4,1157
route__wirelength__iter:4,1030
route__drc_errors,0
route__wirelength,1157
route__vias,400
route__vias__singlecut,400
route__wirelength,1030
route__vias,393
route__vias__singlecut,393
route__vias__multicut,0
design__disconnected_pin__count,17
design__critical_disconnected_pin__count,0
route__wirelength__max,80.12
route__wirelength__max,83.27
timing__unannotated_net__count__corner:nom_tt_025C_1v80,34
timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
timing__unannotated_net__count__corner:nom_ss_100C_1v60,34
Expand All @@ -134,10 +134,10 @@ timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
design__max_slew_violation__count__corner:min_tt_025C_1v80,0
design__max_fanout_violation__count__corner:min_tt_025C_1v80,0
design__max_cap_violation__count__corner:min_tt_025C_1v80,0
clock__skew__worst_hold__corner:min_tt_025C_1v80,0.000486499743149896
clock__skew__worst_setup__corner:min_tt_025C_1v80,0.000486499743149896
timing__hold__ws__corner:min_tt_025C_1v80,0.333317605173373
timing__setup__ws__corner:min_tt_025C_1v80,14.705980849318417
clock__skew__worst_hold__corner:min_tt_025C_1v80,0.001138422721647429
clock__skew__worst_setup__corner:min_tt_025C_1v80,0.001138422721647429
timing__hold__ws__corner:min_tt_025C_1v80,0.32609837975157424
timing__setup__ws__corner:min_tt_025C_1v80,14.70882657305562
timing__hold__tns__corner:min_tt_025C_1v80,0.0
timing__setup__tns__corner:min_tt_025C_1v80,0.0
timing__hold__wns__corner:min_tt_025C_1v80,0
Expand All @@ -153,10 +153,10 @@ timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
design__max_slew_violation__count__corner:min_ss_100C_1v60,0
design__max_fanout_violation__count__corner:min_ss_100C_1v60,0
design__max_cap_violation__count__corner:min_ss_100C_1v60,0
clock__skew__worst_hold__corner:min_ss_100C_1v60,0.0007626677283359677
clock__skew__worst_setup__corner:min_ss_100C_1v60,0.0007626677283359677
timing__hold__ws__corner:min_ss_100C_1v60,0.9271838559356799
timing__setup__ws__corner:min_ss_100C_1v60,13.708269574148412
clock__skew__worst_hold__corner:min_ss_100C_1v60,0.0013118395629984417
clock__skew__worst_setup__corner:min_ss_100C_1v60,0.0013118395629984417
timing__hold__ws__corner:min_ss_100C_1v60,0.9300691036136761
timing__setup__ws__corner:min_ss_100C_1v60,13.713386370169017
timing__hold__tns__corner:min_ss_100C_1v60,0.0
timing__setup__tns__corner:min_ss_100C_1v60,0.0
timing__hold__wns__corner:min_ss_100C_1v60,0
Expand All @@ -172,10 +172,10 @@ timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:min_ff_n40C_1v95,0
design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.00039143689397780595
clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.00039143689397780595
timing__hold__ws__corner:min_ff_n40C_1v95,0.1179136266446428
timing__setup__ws__corner:min_ff_n40C_1v95,15.067844287663679
clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.0010730583392239918
clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.0010730583392239918
timing__hold__ws__corner:min_ff_n40C_1v95,0.10889101040179083
timing__setup__ws__corner:min_ff_n40C_1v95,15.069725449609807
timing__hold__tns__corner:min_ff_n40C_1v95,0.0
timing__setup__tns__corner:min_ff_n40C_1v95,0.0
timing__hold__wns__corner:min_ff_n40C_1v95,0
Expand All @@ -191,10 +191,10 @@ timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
design__max_slew_violation__count__corner:max_tt_025C_1v80,0
design__max_fanout_violation__count__corner:max_tt_025C_1v80,0
design__max_cap_violation__count__corner:max_tt_025C_1v80,0
clock__skew__worst_hold__corner:max_tt_025C_1v80,0.0010008105738532034
clock__skew__worst_setup__corner:max_tt_025C_1v80,0.0010008105738532034
timing__hold__ws__corner:max_tt_025C_1v80,0.3435273829300319
timing__setup__ws__corner:max_tt_025C_1v80,14.69342555882245
clock__skew__worst_hold__corner:max_tt_025C_1v80,0.0017431057091111231
clock__skew__worst_setup__corner:max_tt_025C_1v80,0.0017431057091111231
timing__hold__ws__corner:max_tt_025C_1v80,0.33556303130418236
timing__setup__ws__corner:max_tt_025C_1v80,14.698308763912067
timing__hold__tns__corner:max_tt_025C_1v80,0.0
timing__setup__tns__corner:max_tt_025C_1v80,0.0
timing__hold__wns__corner:max_tt_025C_1v80,0
Expand All @@ -210,10 +210,10 @@ timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
design__max_slew_violation__count__corner:max_ss_100C_1v60,0
design__max_fanout_violation__count__corner:max_ss_100C_1v60,0
design__max_cap_violation__count__corner:max_ss_100C_1v60,0
clock__skew__worst_hold__corner:max_ss_100C_1v60,0.0012515544510563162
clock__skew__worst_setup__corner:max_ss_100C_1v60,0.0012515544510563162
timing__hold__ws__corner:max_ss_100C_1v60,0.9452784378362241
timing__setup__ws__corner:max_ss_100C_1v60,13.688949916616698
clock__skew__worst_hold__corner:max_ss_100C_1v60,0.002018052448935568
clock__skew__worst_setup__corner:max_ss_100C_1v60,0.002018052448935568
timing__hold__ws__corner:max_ss_100C_1v60,0.945075711106194
timing__setup__ws__corner:max_ss_100C_1v60,13.69707941392213
timing__hold__tns__corner:max_ss_100C_1v60,0.0
timing__setup__tns__corner:max_ss_100C_1v60,0.0
timing__hold__wns__corner:max_ss_100C_1v60,0
Expand All @@ -229,10 +229,10 @@ timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:max_ff_n40C_1v95,0
design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.0009384021603164313
clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.0009384021603164313
timing__hold__ws__corner:max_ff_n40C_1v95,0.12491275034558467
timing__setup__ws__corner:max_ff_n40C_1v95,15.058314132950766
clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.0016473350927408176
clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.0016473350927408176
timing__hold__ws__corner:max_ff_n40C_1v95,0.11517728763403584
timing__setup__ws__corner:max_ff_n40C_1v95,15.061735396320211
timing__hold__tns__corner:max_ff_n40C_1v95,0.0
timing__setup__tns__corner:max_ff_n40C_1v95,0.0
timing__hold__wns__corner:max_ff_n40C_1v95,0
Expand All @@ -249,13 +249,13 @@ timing__unannotated_net__count,34
timing__unannotated_net_filtered__count,0
design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79995
design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8
design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000517906
design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000454245
design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000114582
design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000454245
design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000467214
design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000460914
design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000119085
design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000460914
ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
ir__drop__avg,0.000001170000000000000021170673721038202330646527116186916828155517578125
ir__drop__worst,0.000051799999999999998714743376648783623750205151736736297607421875
ir__drop__avg,0.00000119000000000000004144145963891343598106686840765178203582763671875
ir__drop__worst,0.00004669999999999999672206651979422531439922749996185302734375
magic__drc_error__count,0
magic__illegal_overlap__count,0
design__lvs_device_difference__count,0
Expand Down
27 changes: 14 additions & 13 deletions projects/tt_um_senolgulgonul/stats/synthesis-stats.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -2,33 +2,34 @@

=== tt_um_senolgulgonul ===

Number of wires: 38
Number of wire bits: 73
Number of wires: 41
Number of wire bits: 76
Number of public wires: 12
Number of public wire bits: 47
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 54
sky130_fd_sc_hd__a211o_2 1
sky130_fd_sc_hd__a21boi_2 1
sky130_fd_sc_hd__a21o_2 2
Number of cells: 57
sky130_fd_sc_hd__a21o_2 1
sky130_fd_sc_hd__a21oi_2 2
sky130_fd_sc_hd__a31o_2 1
sky130_fd_sc_hd__and2_2 1
sky130_fd_sc_hd__and2b_2 1
sky130_fd_sc_hd__and3_2 2
sky130_fd_sc_hd__and4b_2 1
sky130_fd_sc_hd__buf_2 1
sky130_fd_sc_hd__conb_1 16
sky130_fd_sc_hd__dfrtp_2 11
sky130_fd_sc_hd__inv_2 4
sky130_fd_sc_hd__mux2_1 3
sky130_fd_sc_hd__nand2_2 2
sky130_fd_sc_hd__nand2b_2 1
sky130_fd_sc_hd__nor2_2 1
sky130_fd_sc_hd__o211a_2 1
sky130_fd_sc_hd__mux2_1 2
sky130_fd_sc_hd__nor2_2 7
sky130_fd_sc_hd__nor3_2 1
sky130_fd_sc_hd__o21a_2 1
sky130_fd_sc_hd__o21ba_2 1
sky130_fd_sc_hd__or3_2 2
sky130_fd_sc_hd__o22a_2 1
sky130_fd_sc_hd__o31ai_2 1
sky130_fd_sc_hd__or2_2 1
sky130_fd_sc_hd__xnor2_2 1

Chip area for module '\tt_um_senolgulgonul': 569.296000
Chip area for module '\tt_um_senolgulgonul': 586.812800

Binary file modified projects/tt_um_senolgulgonul/tt_um_senolgulgonul.gds
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