feat: update project tt_um_MichaelBell_rle_vga from MichaelBell/tt09-…

…rle-vga

Commit: f432bf60b6c9c29653fb6a307d741fc6c26792f1
Workflow: https://github.com/MichaelBell/tt09-rle-vga/actions/runs/11765436163

projects/tt_um_MichaelBell_rle_vga/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout tt09 a48b1c74",
   "repo": "https://github.com/MichaelBell/tt09-rle-vga",
-  "commit": "d8d2ede5023125bee520ffe2c8143db3fcdca338",
-  "workflow_url": "https://github.com/MichaelBell/tt09-rle-vga/actions/runs/11758514898",
+  "commit": "f432bf60b6c9c29653fb6a307d741fc6c26792f1",
+  "workflow_url": "https://github.com/MichaelBell/tt09-rle-vga/actions/runs/11765436163",
   "sort_id": 1731178374234,
   "openlane_version": "OpenLane2 2.1.9",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"

projects/tt_um_MichaelBell_rle_vga/stats/metrics.csv

@@ -3,21 +3,21 @@ design__lint_error__count,0
 design__lint_timing_construct__count,0
 design__lint_warning__count,5
 design__inferred_latch__count,0
-design__instance__count,1139
-design__instance__area,9768.12
+design__instance__count,1240
+design__instance__area,10974.3
 design__instance_unmapped__count,0
 synthesis__check_error__count,0
 design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
-design__max_fanout_violation__count__corner:nom_tt_025C_1v80,8
+design__max_fanout_violation__count__corner:nom_tt_025C_1v80,10
 design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
-power__internal__total,0.000845464994199574
-power__switching__total,0.0006071382667869329
-power__leakage__total,1.1413195721843294E-8
-power__total,0.001452614669688046
-clock__skew__worst_hold__corner:nom_tt_025C_1v80,-0.030926873048991145
-clock__skew__worst_setup__corner:nom_tt_025C_1v80,-0.030926873048991145
-timing__hold__ws__corner:nom_tt_025C_1v80,0.3063630547076844
-timing__setup__ws__corner:nom_tt_025C_1v80,6.051938677051545
+power__internal__total,0.0009800225961953402
+power__switching__total,0.0007693151128478348
+power__leakage__total,1.2590991360639237E-8
+power__total,0.0017493502236902714
+clock__skew__worst_hold__corner:nom_tt_025C_1v80,-0.041229576475439254
+clock__skew__worst_setup__corner:nom_tt_025C_1v80,-0.041229576475439254
+timing__hold__ws__corner:nom_tt_025C_1v80,0.3254485106857304
+timing__setup__ws__corner:nom_tt_025C_1v80,6.032518655355566
 timing__hold__tns__corner:nom_tt_025C_1v80,0.0
 timing__setup__tns__corner:nom_tt_025C_1v80,0.0
 timing__hold__wns__corner:nom_tt_025C_1v80,0
@@ -28,13 +28,13 @@ timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80,0
 timing__setup_vio__count__corner:nom_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:nom_tt_025C_1v80,Infinity
 timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
-design__max_slew_violation__count__corner:nom_ss_100C_1v60,4
-design__max_fanout_violation__count__corner:nom_ss_100C_1v60,8
+design__max_slew_violation__count__corner:nom_ss_100C_1v60,0
+design__max_fanout_violation__count__corner:nom_ss_100C_1v60,10
 design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
-clock__skew__worst_hold__corner:nom_ss_100C_1v60,-0.0262490037135851
-clock__skew__worst_setup__corner:nom_ss_100C_1v60,-0.0262490037135851
-timing__hold__ws__corner:nom_ss_100C_1v60,0.817236412784929
-timing__setup__ws__corner:nom_ss_100C_1v60,5.099496969035546
+clock__skew__worst_hold__corner:nom_ss_100C_1v60,-0.03902367428542436
+clock__skew__worst_setup__corner:nom_ss_100C_1v60,-0.03902367428542436
+timing__hold__ws__corner:nom_ss_100C_1v60,0.8717394830512794
+timing__setup__ws__corner:nom_ss_100C_1v60,5.0643597415800405
 timing__hold__tns__corner:nom_ss_100C_1v60,0.0
 timing__setup__tns__corner:nom_ss_100C_1v60,0.0
 timing__hold__wns__corner:nom_ss_100C_1v60,0
@@ -46,12 +46,12 @@ timing__setup_vio__count__corner:nom_ss_100C_1v60,0
 timing__setup_r2r__ws__corner:nom_ss_100C_1v60,Infinity
 timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
 design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0
-design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,8
+design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,10
 design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
-clock__skew__worst_hold__corner:nom_ff_n40C_1v95,-0.025662972473462616
-clock__skew__worst_setup__corner:nom_ff_n40C_1v95,-0.025662972473462616
-timing__hold__ws__corner:nom_ff_n40C_1v95,0.11398765587392928
-timing__setup__ws__corner:nom_ff_n40C_1v95,6.436171777708031
+clock__skew__worst_hold__corner:nom_ff_n40C_1v95,-0.033587772402941245
+clock__skew__worst_setup__corner:nom_ff_n40C_1v95,-0.033587772402941245
+timing__hold__ws__corner:nom_ff_n40C_1v95,0.11939860549322825
+timing__setup__ws__corner:nom_ff_n40C_1v95,6.419946533878068
 timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
 timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
 timing__hold__wns__corner:nom_ff_n40C_1v95,0
@@ -62,13 +62,13 @@ timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95,0
 timing__setup_vio__count__corner:nom_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,Infinity
 timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
-design__max_slew_violation__count,4
-design__max_fanout_violation__count,8
+design__max_slew_violation__count,0
+design__max_fanout_violation__count,10
 design__max_cap_violation__count,0
-clock__skew__worst_hold,-0.022019608981660114
-clock__skew__worst_setup,-0.03326489178267295
-timing__hold__ws,0.1107364231655146
-timing__setup__ws,5.076889274901109
+clock__skew__worst_hold,-0.03021569191487831
+clock__skew__worst_setup,-0.04339384530085324
+timing__hold__ws,0.11610285284026699
+timing__setup__ws,5.037383097675537
 timing__hold__tns,0.0
 timing__setup__tns,0.0
 timing__hold__wns,0
@@ -86,12 +86,12 @@ flow__errors__count,0
 design__io,45
 design__die__area,17954.7
 design__core__area,16493.3
-design__instance__count__stdcell,1139
-design__instance__area__stdcell,9768.12
+design__instance__count__stdcell,1240
+design__instance__area__stdcell,10974.3
 design__instance__count__macros,0
 design__instance__area__macros,0
-design__instance__utilization,0.592247
-design__instance__utilization__stdcell,0.592247
+design__instance__utilization,0.665377
+design__instance__utilization__stdcell,0.665377
 design__power_grid_violation__count__net:VPWR,0
 design__power_grid_violation__count__net:VGND,0
 design__power_grid_violation__count,0
@@ -100,46 +100,46 @@ timing__drv__floating__pins,0
 design__instance__displacement__total,0
 design__instance__displacement__mean,0
 design__instance__displacement__max,0
-route__wirelength__estimated,18581.3
+route__wirelength__estimated,22674.4
 design__violations,0
 design__instance__count__setup_buffer,0
-design__instance__count__hold_buffer,108
+design__instance__count__hold_buffer,122
 antenna__violating__nets,1
 antenna__violating__pins,1
 route__antenna_violation__count,1
-route__net,917
+route__net,1018
 route__net__special,2
-route__drc_errors__iter:1,574
-route__wirelength__iter:1,21544
-route__drc_errors__iter:2,224
-route__wirelength__iter:2,21073
-route__drc_errors__iter:3,152
-route__wirelength__iter:3,20948
-route__drc_errors__iter:4,7
-route__wirelength__iter:4,20892
+route__drc_errors__iter:1,690
+route__wirelength__iter:1,26690
+route__drc_errors__iter:2,335
+route__wirelength__iter:2,26298
+route__drc_errors__iter:3,276
+route__wirelength__iter:3,26130
+route__drc_errors__iter:4,54
+route__wirelength__iter:4,26081
 route__drc_errors__iter:5,0
-route__wirelength__iter:5,20898
+route__wirelength__iter:5,26064
 route__drc_errors,0
-route__wirelength,20898
-route__vias,6442
-route__vias__singlecut,6442
+route__wirelength,26064
+route__vias,7333
+route__vias__singlecut,7333
 route__vias__multicut,0
 design__disconnected_pin__count,8
 design__critical_disconnected_pin__count,0
-route__wirelength__max,268.58
+route__wirelength__max,282.8
 timing__unannotated_net__count__corner:nom_tt_025C_1v80,29
 timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
 timing__unannotated_net__count__corner:nom_ss_100C_1v60,29
 timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0
 timing__unannotated_net__count__corner:nom_ff_n40C_1v95,29
 timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
 design__max_slew_violation__count__corner:min_tt_025C_1v80,0
-design__max_fanout_violation__count__corner:min_tt_025C_1v80,8
+design__max_fanout_violation__count__corner:min_tt_025C_1v80,10
 design__max_cap_violation__count__corner:min_tt_025C_1v80,0
-clock__skew__worst_hold__corner:min_tt_025C_1v80,-0.02781053244188343
-clock__skew__worst_setup__corner:min_tt_025C_1v80,-0.02781053244188343
-timing__hold__ws__corner:min_tt_025C_1v80,0.3014824031310955
-timing__setup__ws__corner:min_tt_025C_1v80,6.066863627638292
+clock__skew__worst_hold__corner:min_tt_025C_1v80,-0.035977721820068594
+clock__skew__worst_setup__corner:min_tt_025C_1v80,-0.035977721820068594
+timing__hold__ws__corner:min_tt_025C_1v80,0.317979263031715
+timing__setup__ws__corner:min_tt_025C_1v80,6.048790972643105
 timing__hold__tns__corner:min_tt_025C_1v80,0.0
 timing__setup__tns__corner:min_tt_025C_1v80,0.0
 timing__hold__wns__corner:min_tt_025C_1v80,0
@@ -152,13 +152,13 @@ timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity
 timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
 timing__unannotated_net__count__corner:min_tt_025C_1v80,29
 timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
-design__max_slew_violation__count__corner:min_ss_100C_1v60,4
-design__max_fanout_violation__count__corner:min_ss_100C_1v60,8
+design__max_slew_violation__count__corner:min_ss_100C_1v60,0
+design__max_fanout_violation__count__corner:min_ss_100C_1v60,10
 design__max_cap_violation__count__corner:min_ss_100C_1v60,0
-clock__skew__worst_hold__corner:min_ss_100C_1v60,-0.022019608981660114
-clock__skew__worst_setup__corner:min_ss_100C_1v60,-0.022019608981660114
-timing__hold__ws__corner:min_ss_100C_1v60,0.8084406706235756
-timing__setup__ws__corner:min_ss_100C_1v60,5.123760227791125
+clock__skew__worst_hold__corner:min_ss_100C_1v60,-0.03203354339123628
+clock__skew__worst_setup__corner:min_ss_100C_1v60,-0.03203354339123628
+timing__hold__ws__corner:min_ss_100C_1v60,0.8650834737858017
+timing__setup__ws__corner:min_ss_100C_1v60,5.093058563489049
 timing__hold__tns__corner:min_ss_100C_1v60,0.0
 timing__setup__tns__corner:min_ss_100C_1v60,0.0
 timing__hold__wns__corner:min_ss_100C_1v60,0
@@ -172,12 +172,12 @@ timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
 timing__unannotated_net__count__corner:min_ss_100C_1v60,29
 timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
 design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
-design__max_fanout_violation__count__corner:min_ff_n40C_1v95,8
+design__max_fanout_violation__count__corner:min_ff_n40C_1v95,10
 design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
-clock__skew__worst_hold__corner:min_ff_n40C_1v95,-0.023638397464072904
-clock__skew__worst_setup__corner:min_ff_n40C_1v95,-0.023638397464072904
-timing__hold__ws__corner:min_ff_n40C_1v95,0.1107364231655146
-timing__setup__ws__corner:min_ff_n40C_1v95,6.446878768860331
+clock__skew__worst_hold__corner:min_ff_n40C_1v95,-0.03021569191487831
+clock__skew__worst_setup__corner:min_ff_n40C_1v95,-0.03021569191487831
+timing__hold__ws__corner:min_ff_n40C_1v95,0.11610285284026699
+timing__setup__ws__corner:min_ff_n40C_1v95,6.432826897684841
 timing__hold__tns__corner:min_ff_n40C_1v95,0.0
 timing__setup__tns__corner:min_ff_n40C_1v95,0.0
 timing__hold__wns__corner:min_ff_n40C_1v95,0
@@ -191,12 +191,12 @@ timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
 timing__unannotated_net__count__corner:min_ff_n40C_1v95,29
 timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
 design__max_slew_violation__count__corner:max_tt_025C_1v80,0
-design__max_fanout_violation__count__corner:max_tt_025C_1v80,8
+design__max_fanout_violation__count__corner:max_tt_025C_1v80,10
 design__max_cap_violation__count__corner:max_tt_025C_1v80,0
-clock__skew__worst_hold__corner:max_tt_025C_1v80,-0.03326489178267295
-clock__skew__worst_setup__corner:max_tt_025C_1v80,-0.03326489178267295
-timing__hold__ws__corner:max_tt_025C_1v80,0.31086423204372415
-timing__setup__ws__corner:max_tt_025C_1v80,6.03948907979051
+clock__skew__worst_hold__corner:max_tt_025C_1v80,-0.04339384530085324
+clock__skew__worst_setup__corner:max_tt_025C_1v80,-0.04339384530085324
+timing__hold__ws__corner:max_tt_025C_1v80,0.3295560029261039
+timing__setup__ws__corner:max_tt_025C_1v80,6.015648593974664
 timing__hold__tns__corner:max_tt_025C_1v80,0.0
 timing__setup__tns__corner:max_tt_025C_1v80,0.0
 timing__hold__wns__corner:max_tt_025C_1v80,0
@@ -209,13 +209,13 @@ timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity
 timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
 timing__unannotated_net__count__corner:max_tt_025C_1v80,29
 timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
-design__max_slew_violation__count__corner:max_ss_100C_1v60,4
-design__max_fanout_violation__count__corner:max_ss_100C_1v60,8
+design__max_slew_violation__count__corner:max_ss_100C_1v60,0
+design__max_fanout_violation__count__corner:max_ss_100C_1v60,10
 design__max_cap_violation__count__corner:max_ss_100C_1v60,0
-clock__skew__worst_hold__corner:max_ss_100C_1v60,-0.02906847067551189
-clock__skew__worst_setup__corner:max_ss_100C_1v60,-0.02906847067551189
-timing__hold__ws__corner:max_ss_100C_1v60,0.825120772839592
-timing__setup__ws__corner:max_ss_100C_1v60,5.076889274901109
+clock__skew__worst_hold__corner:max_ss_100C_1v60,-0.0429323810876167
+clock__skew__worst_setup__corner:max_ss_100C_1v60,-0.0429323810876167
+timing__hold__ws__corner:max_ss_100C_1v60,0.8799448085914389
+timing__setup__ws__corner:max_ss_100C_1v60,5.037383097675537
 timing__hold__tns__corner:max_ss_100C_1v60,0.0
 timing__setup__tns__corner:max_ss_100C_1v60,0.0
 timing__hold__wns__corner:max_ss_100C_1v60,0
@@ -229,12 +229,12 @@ timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
 timing__unannotated_net__count__corner:max_ss_100C_1v60,29
 timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
 design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
-design__max_fanout_violation__count__corner:max_ff_n40C_1v95,8
+design__max_fanout_violation__count__corner:max_ff_n40C_1v95,10
 design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
-clock__skew__worst_hold__corner:max_ff_n40C_1v95,-0.027295361188311704
-clock__skew__worst_setup__corner:max_ff_n40C_1v95,-0.027295361188311704
-timing__hold__ws__corner:max_ff_n40C_1v95,0.11731671521857127
-timing__setup__ws__corner:max_ff_n40C_1v95,6.425450575700615
+clock__skew__worst_hold__corner:max_ff_n40C_1v95,-0.034805131983872015
+clock__skew__worst_setup__corner:max_ff_n40C_1v95,-0.034805131983872015
+timing__hold__ws__corner:max_ff_n40C_1v95,0.12228080005782041
+timing__setup__ws__corner:max_ff_n40C_1v95,6.406572342855975
 timing__hold__tns__corner:max_ff_n40C_1v95,0.0
 timing__setup__tns__corner:max_ff_n40C_1v95,0.0
 timing__hold__wns__corner:max_ff_n40C_1v95,0
@@ -250,14 +250,14 @@ timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0
 timing__unannotated_net__count,29
 timing__unannotated_net_filtered__count,0
 design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79991
-design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.79998
-design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000857885
-design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000886688
-design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.0000248277
-design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000886688
+design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.79997
+design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000925215
+design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000983346
+design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.0000289277
+design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000983346
 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
-ir__drop__avg,0.0000246000000000000016396606294932780656381510198116302490234375
-ir__drop__worst,0.00008579999999999999844672859961036692766356281936168670654296875
+ir__drop__avg,0.00003009999999999999980258846843383935265592299401760101318359375
+ir__drop__worst,0.00009249999999999999867293654087774257277487777173519134521484375
 magic__drc_error__count,0
 magic__illegal_overlap__count,0
 design__lvs_device_difference__count,0