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feat: update project tt_um_wokwi_413923150973445121 from MarianoMunoz…
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Commit: efb92d8a8ff5def23657bc929f13ac7b45e5dc24
Workflow: https://github.com/MarianoMunoz/tt00-wowki-design/actions/runs/11764430515
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@TinyTapeoutBot @urish
TinyTapeoutBot authored and urish committed Nov 10, 2024
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4 changes: 2 additions & 2 deletions projects/tt_um_wokwi_413923150973445121/commit_id.json
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
{
"app": "Tiny Tapeout tt09 a48b1c74",
"repo": "https://github.com/MarianoMunoz/tt00-wowki-design",
"commit": "d0a76e4311028c478f725d4c6854c3f4a047324a",
"workflow_url": "https://github.com/MarianoMunoz/tt00-wowki-design/actions/runs/11761518106",
"commit": "efb92d8a8ff5def23657bc929f13ac7b45e5dc24",
"workflow_url": "https://github.com/MarianoMunoz/tt00-wowki-design/actions/runs/11764430515",
"sort_id": 1731012978166,
"openlane_version": "OpenLane2 2.1.9",
"pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"
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6 changes: 3 additions & 3 deletions projects/tt_um_wokwi_413923150973445121/docs/info.md
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Original file line number Diff line number Diff line change
Expand Up @@ -9,12 +9,12 @@ You can also include images in this folder and reference them in the markdown. E

## How it works

Logic test
Binary counter using flip flops connected to clock line. Displays numbers on the seven segment display.

## How to test

Have fun and play
Use the step button to count from zero to nine.

## External hardware

number led array and buttons
number led array and step button
30 changes: 15 additions & 15 deletions projects/tt_um_wokwi_413923150973445121/info.yaml
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Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
# Tiny Tapeout project information (Wokwi project)
project:
wokwi_id: 413923150973445121 # Set this to the ID of your Wokwi project (the number from the project's URL)
title: "design00" # Project title
title: "Zero to Nine Display Count" # Project title
author: "Mariano" # Your name
discord: "" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
description: "First Design" # One line description of what your project does
description: "First Design. Display numbers on seven segment display using flip flop counter." # One line description of what your project does
language: "Wokwi" # other examples include SystemVerilog, Amaranth, VHDL, etc
clock_hz: 0 # Clock frequency in Hz (or 0 if not applicable)

Expand All @@ -15,24 +15,24 @@ project:
# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
pinout:
# Inputs
ui[0]: "IN0"
ui[1]: "IN1"
ui[2]: "IN2"
ui[3]: "IN3"
ui[4]: "IN4"
ui[5]: "IN5"
ui[6]: "IN6"
ui[7]: "IN7"
ui[0]: ""
ui[1]: ""
ui[2]: ""
ui[3]: ""
ui[4]: ""
ui[5]: ""
ui[6]: ""
ui[7]: ""

# Outputs
uo[0]: "OUT0"
uo[1]: "OUT1"
uo[2]: "OUT2"
uo[3]: ""
uo[4]: ""
uo[5]: ""
uo[6]: ""
uo[7]: ""
uo[3]: "OUT3"
uo[4]: "OUT4"
uo[5]: "OUT5"
uo[6]: "OUT6"
uo[7]: "OUT7"

# Bidirectional pins
uio[0]: ""
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110 changes: 55 additions & 55 deletions projects/tt_um_wokwi_413923150973445121/stats/metrics.csv
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Original file line number Diff line number Diff line change
Expand Up @@ -3,21 +3,21 @@ design__lint_error__count,0
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power__internal__total,0.0000023479888113797642
power__switching__total,0.0
power__leakage__total,1.6269392499879132E-9
power__total,0.0000023496156700275606
power__leakage__total,1.7734165247418332E-9
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clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.0
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timing__setup__ws__corner:nom_tt_025C_1v80,13.846090887966392
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timing__setup__tns__corner:nom_tt_025C_1v80,0.0
timing__hold__wns__corner:nom_tt_025C_1v80,0
Expand All @@ -33,8 +33,8 @@ design__max_fanout_violation__count__corner:nom_ss_100C_1v60,0
design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.0
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timing__hold__wns__corner:nom_ss_100C_1v60,0
Expand All @@ -50,8 +50,8 @@ design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,0
design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
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timing__setup__ws__corner:nom_ff_n40C_1v95,14.523472613406232
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Expand All @@ -67,8 +67,8 @@ design__max_fanout_violation__count,0
design__max_cap_violation__count,0
clock__skew__worst_hold,0.0
clock__skew__worst_setup,0.0
timing__hold__ws,0.3602139799509259
timing__setup__ws,12.273434171932918
timing__hold__ws,0.39918122714952786
timing__setup__ws,11.849390248844285
timing__hold__tns,0.0
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timing__hold__wns,0
Expand All @@ -86,12 +86,12 @@ flow__errors__count,0
design__io,45
design__die__area,17954.7
design__core__area,16493.3
design__instance__count__stdcell,287
design__instance__area__stdcell,659.382
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design__instance__utilization__stdcell,0.0399788
design__instance__utilization,0.0497648
design__instance__utilization__stdcell,0.0497648
design__power_grid_violation__count__net:VGND,0
design__power_grid_violation__count__net:VPWR,0
design__power_grid_violation__count,0
Expand All @@ -100,42 +100,42 @@ timing__drv__floating__pins,0
design__instance__displacement__total,0
design__instance__displacement__mean,0
design__instance__displacement__max,0
route__wirelength__estimated,574.535
route__wirelength__estimated,773.934
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route__antenna_violation__count,0
route__net,81
route__net,109
route__net__special,2
route__drc_errors__iter:1,36
route__wirelength__iter:1,594
route__drc_errors__iter:2,1
route__wirelength__iter:2,548
route__drc_errors__iter:1,49
route__wirelength__iter:1,832
route__drc_errors__iter:2,7
route__wirelength__iter:2,821
route__drc_errors__iter:3,0
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route__wirelength__iter:3,802
route__drc_errors,0
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route__vias,302
route__vias__singlecut,302
route__wirelength,802
route__vias,433
route__vias__singlecut,433
route__vias__multicut,0
design__disconnected_pin__count,18
design__critical_disconnected_pin__count,0
route__wirelength__max,45.28
timing__unannotated_net__count__corner:nom_tt_025C_1v80,74
route__wirelength__max,82.225
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design__max_slew_violation__count__corner:min_tt_025C_1v80,0
design__max_fanout_violation__count__corner:min_tt_025C_1v80,0
design__max_cap_violation__count__corner:min_tt_025C_1v80,0
clock__skew__worst_hold__corner:min_tt_025C_1v80,0.0
clock__skew__worst_setup__corner:min_tt_025C_1v80,0.0
timing__hold__ws__corner:min_tt_025C_1v80,0.6856978512409907
timing__setup__ws__corner:min_tt_025C_1v80,14.092873045216388
timing__hold__ws__corner:min_tt_025C_1v80,0.7285897646982152
timing__setup__ws__corner:min_tt_025C_1v80,13.8463724405334
timing__hold__tns__corner:min_tt_025C_1v80,0.0
timing__setup__tns__corner:min_tt_025C_1v80,0.0
timing__hold__wns__corner:min_tt_025C_1v80,0
Expand All @@ -146,15 +146,15 @@ timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
timing__setup_vio__count__corner:min_tt_025C_1v80,0
timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
timing__unannotated_net__count__corner:min_tt_025C_1v80,74
timing__unannotated_net__count__corner:min_tt_025C_1v80,102
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design__max_slew_violation__count__corner:min_ss_100C_1v60,0
design__max_fanout_violation__count__corner:min_ss_100C_1v60,0
design__max_cap_violation__count__corner:min_ss_100C_1v60,0
clock__skew__worst_hold__corner:min_ss_100C_1v60,0.0
clock__skew__worst_setup__corner:min_ss_100C_1v60,0.0
timing__hold__ws__corner:min_ss_100C_1v60,1.6259736239867688
timing__setup__ws__corner:min_ss_100C_1v60,12.27428415870461
timing__hold__ws__corner:min_ss_100C_1v60,1.6943389393306398
timing__setup__ws__corner:min_ss_100C_1v60,11.850398331379155
timing__hold__tns__corner:min_ss_100C_1v60,0.0
timing__setup__tns__corner:min_ss_100C_1v60,0.0
timing__hold__wns__corner:min_ss_100C_1v60,0
Expand All @@ -165,15 +165,15 @@ timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
timing__setup_vio__count__corner:min_ss_100C_1v60,0
timing__setup_r2r__ws__corner:min_ss_100C_1v60,Infinity
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design__max_fanout_violation__count__corner:min_ff_n40C_1v95,0
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clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.0
clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.0
timing__hold__ws__corner:min_ff_n40C_1v95,0.3602139799509259
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timing__setup__ws__corner:min_ff_n40C_1v95,14.523731073333675
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Expand All @@ -184,15 +184,15 @@ timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
timing__setup_vio__count__corner:min_ff_n40C_1v95,0
timing__setup_r2r__ws__corner:min_ff_n40C_1v95,Infinity
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design__max_fanout_violation__count__corner:max_tt_025C_1v80,0
design__max_cap_violation__count__corner:max_tt_025C_1v80,0
clock__skew__worst_hold__corner:max_tt_025C_1v80,0.0
clock__skew__worst_setup__corner:max_tt_025C_1v80,0.0
timing__hold__ws__corner:max_tt_025C_1v80,0.6856978512409907
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timing__setup__ws__corner:max_tt_025C_1v80,13.845551763650386
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timing__setup__tns__corner:max_tt_025C_1v80,0.0
timing__hold__wns__corner:max_tt_025C_1v80,0
Expand All @@ -203,15 +203,15 @@ timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
timing__setup_vio__count__corner:max_tt_025C_1v80,0
timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity
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design__max_slew_violation__count__corner:max_ss_100C_1v60,0
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clock__skew__worst_hold__corner:max_ss_100C_1v60,0.0
clock__skew__worst_setup__corner:max_ss_100C_1v60,0.0
timing__hold__ws__corner:max_ss_100C_1v60,1.6259736239867688
timing__setup__ws__corner:max_ss_100C_1v60,12.273434171932918
timing__hold__ws__corner:max_ss_100C_1v60,1.6943389393306398
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timing__setup__tns__corner:max_ss_100C_1v60,0.0
timing__hold__wns__corner:max_ss_100C_1v60,0
Expand All @@ -222,15 +222,15 @@ timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
timing__setup_vio__count__corner:max_ss_100C_1v60,0
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Expand All @@ -241,19 +241,19 @@ timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
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Expand Down
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