feat: update project tt_um_wokwi_413923150973445121 from MarianoMunoz…

…/tt00-wowki-design

Commit: d0a76e4311028c478f725d4c6854c3f4a047324a
Workflow: https://github.com/MarianoMunoz/tt00-wowki-design/actions/runs/11761518106

projects/tt_um_wokwi_413923150973445121/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout tt09 a48b1c74",
   "repo": "https://github.com/MarianoMunoz/tt00-wowki-design",
-  "commit": "0a9fe0f8af23e73b83e2dbb88da4bd3c1b55d331",
-  "workflow_url": "https://github.com/MarianoMunoz/tt00-wowki-design/actions/runs/11729901102",
+  "commit": "d0a76e4311028c478f725d4c6854c3f4a047324a",
+  "workflow_url": "https://github.com/MarianoMunoz/tt00-wowki-design/actions/runs/11761518106",
   "sort_id": 1731012978166,
   "openlane_version": "OpenLane2 2.1.9",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"

projects/tt_um_wokwi_413923150973445121/stats/metrics.csv

@@ -3,21 +3,21 @@ design__lint_error__count,0
 design__lint_timing_construct__count,0
 design__lint_warning__count,0
 design__inferred_latch__count,0
-design__instance__count,255
-design__instance__area,410.394
+design__instance__count,287
+design__instance__area,659.382
 design__instance_unmapped__count,0
 synthesis__check_error__count,0
 design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:nom_tt_025C_1v80,0
 design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
-power__internal__total,7.980143550412322E-7
-power__switching__total,0.000001861507371359039
-power__leakage__total,1.3475258686668212E-9
-power__total,0.000002660869085957529
+power__internal__total,0.0000023479888113797642
+power__switching__total,0.0
+power__leakage__total,1.6269392499879132E-9
+power__total,0.0000023496156700275606
 clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.0
 clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.0
-timing__hold__ws__corner:nom_tt_025C_1v80,7.932996706301259
-timing__setup__ws__corner:nom_tt_025C_1v80,11.357979767072983
+timing__hold__ws__corner:nom_tt_025C_1v80,0.6856978512409907
+timing__setup__ws__corner:nom_tt_025C_1v80,14.092686527742975
 timing__hold__tns__corner:nom_tt_025C_1v80,0.0
 timing__setup__tns__corner:nom_tt_025C_1v80,0.0
 timing__hold__wns__corner:nom_tt_025C_1v80,0
@@ -33,8 +33,8 @@ design__max_fanout_violation__count__corner:nom_ss_100C_1v60,0
 design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
 clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.0
 clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.0
-timing__hold__ws__corner:nom_ss_100C_1v60,8.10584156073381
-timing__setup__ws__corner:nom_ss_100C_1v60,10.98903399380873
+timing__hold__ws__corner:nom_ss_100C_1v60,1.6259736239867688
+timing__setup__ws__corner:nom_ss_100C_1v60,12.27398040167648
 timing__hold__tns__corner:nom_ss_100C_1v60,0.0
 timing__setup__tns__corner:nom_ss_100C_1v60,0.0
 timing__hold__wns__corner:nom_ss_100C_1v60,0
@@ -50,8 +50,8 @@ design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.0
 clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.0
-timing__hold__ws__corner:nom_ff_n40C_1v95,7.869280561026796
-timing__setup__ws__corner:nom_ff_n40C_1v95,11.492220833579895
+timing__hold__ws__corner:nom_ff_n40C_1v95,0.3602139799509259
+timing__setup__ws__corner:nom_ff_n40C_1v95,14.693426447000894
 timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
 timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
 timing__hold__wns__corner:nom_ff_n40C_1v95,0
@@ -67,8 +67,8 @@ design__max_fanout_violation__count,0
 design__max_cap_violation__count,0
 clock__skew__worst_hold,0.0
 clock__skew__worst_setup,0.0
-timing__hold__ws,7.868014018564484
-timing__setup__ws,10.986471598995426
+timing__hold__ws,0.3602139799509259
+timing__setup__ws,12.273434171932918
 timing__hold__tns,0.0
 timing__setup__tns,0.0
 timing__hold__wns,0
@@ -86,12 +86,12 @@ flow__errors__count,0
 design__io,45
 design__die__area,17954.7
 design__core__area,16493.3
-design__instance__count__stdcell,255
-design__instance__area__stdcell,410.394
+design__instance__count__stdcell,287
+design__instance__area__stdcell,659.382
 design__instance__count__macros,0
 design__instance__area__macros,0
-design__instance__utilization,0.0248824
-design__instance__utilization__stdcell,0.0248824
+design__instance__utilization,0.0399788
+design__instance__utilization__stdcell,0.0399788
 design__power_grid_violation__count__net:VGND,0
 design__power_grid_violation__count__net:VPWR,0
 design__power_grid_violation__count,0
@@ -100,40 +100,42 @@ timing__drv__floating__pins,0
 design__instance__displacement__total,0
 design__instance__displacement__mean,0
 design__instance__displacement__max,0
-route__wirelength__estimated,378.852
+route__wirelength__estimated,574.535
 design__violations,0
 design__instance__count__setup_buffer,0
-design__instance__count__hold_buffer,0
+design__instance__count__hold_buffer,1
 antenna__violating__nets,0
 antenna__violating__pins,0
 route__antenna_violation__count,0
-route__net,49
+route__net,81
 route__net__special,2
-route__drc_errors__iter:1,31
-route__wirelength__iter:1,426
-route__drc_errors__iter:2,0
-route__wirelength__iter:2,386
+route__drc_errors__iter:1,36
+route__wirelength__iter:1,594
+route__drc_errors__iter:2,1
+route__wirelength__iter:2,548
+route__drc_errors__iter:3,0
+route__wirelength__iter:3,544
 route__drc_errors,0
-route__wirelength,386
-route__vias,138
-route__vias__singlecut,138
+route__wirelength,544
+route__vias,302
+route__vias__singlecut,302
 route__vias__multicut,0
-design__disconnected_pin__count,12
+design__disconnected_pin__count,18
 design__critical_disconnected_pin__count,0
-route__wirelength__max,67.39
-timing__unannotated_net__count__corner:nom_tt_025C_1v80,37
-timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
-timing__unannotated_net__count__corner:nom_ss_100C_1v60,37
-timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0
-timing__unannotated_net__count__corner:nom_ff_n40C_1v95,37
-timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
+route__wirelength__max,45.28
+timing__unannotated_net__count__corner:nom_tt_025C_1v80,74
+timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,1
+timing__unannotated_net__count__corner:nom_ss_100C_1v60,74
+timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,1
+timing__unannotated_net__count__corner:nom_ff_n40C_1v95,74
+timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,1
 design__max_slew_violation__count__corner:min_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:min_tt_025C_1v80,0
 design__max_cap_violation__count__corner:min_tt_025C_1v80,0
 clock__skew__worst_hold__corner:min_tt_025C_1v80,0.0
 clock__skew__worst_setup__corner:min_tt_025C_1v80,0.0
-timing__hold__ws__corner:min_tt_025C_1v80,7.931241665694296
-timing__setup__ws__corner:min_tt_025C_1v80,11.359196571542386
+timing__hold__ws__corner:min_tt_025C_1v80,0.6856978512409907
+timing__setup__ws__corner:min_tt_025C_1v80,14.092873045216388
 timing__hold__tns__corner:min_tt_025C_1v80,0.0
 timing__setup__tns__corner:min_tt_025C_1v80,0.0
 timing__hold__wns__corner:min_tt_025C_1v80,0
@@ -144,15 +146,15 @@ timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
 timing__setup_vio__count__corner:min_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity
 timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
-timing__unannotated_net__count__corner:min_tt_025C_1v80,37
-timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
+timing__unannotated_net__count__corner:min_tt_025C_1v80,74
+timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,1
 design__max_slew_violation__count__corner:min_ss_100C_1v60,0
 design__max_fanout_violation__count__corner:min_ss_100C_1v60,0
 design__max_cap_violation__count__corner:min_ss_100C_1v60,0
 clock__skew__worst_hold__corner:min_ss_100C_1v60,0.0
 clock__skew__worst_setup__corner:min_ss_100C_1v60,0.0
-timing__hold__ws__corner:min_ss_100C_1v60,8.102571287699982
-timing__setup__ws__corner:min_ss_100C_1v60,10.990971999175326
+timing__hold__ws__corner:min_ss_100C_1v60,1.6259736239867688
+timing__setup__ws__corner:min_ss_100C_1v60,12.27428415870461
 timing__hold__tns__corner:min_ss_100C_1v60,0.0
 timing__setup__tns__corner:min_ss_100C_1v60,0.0
 timing__hold__wns__corner:min_ss_100C_1v60,0
@@ -163,15 +165,15 @@ timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
 timing__setup_vio__count__corner:min_ss_100C_1v60,0
 timing__setup_r2r__ws__corner:min_ss_100C_1v60,Infinity
 timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
-timing__unannotated_net__count__corner:min_ss_100C_1v60,37
-timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
+timing__unannotated_net__count__corner:min_ss_100C_1v60,74
+timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,1
 design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
 design__max_fanout_violation__count__corner:min_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.0
 clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.0
-timing__hold__ws__corner:min_ff_n40C_1v95,7.868014018564484
-timing__setup__ws__corner:min_ff_n40C_1v95,11.493163190909849
+timing__hold__ws__corner:min_ff_n40C_1v95,0.3602139799509259
+timing__setup__ws__corner:min_ff_n40C_1v95,14.693610299938971
 timing__hold__tns__corner:min_ff_n40C_1v95,0.0
 timing__setup__tns__corner:min_ff_n40C_1v95,0.0
 timing__hold__wns__corner:min_ff_n40C_1v95,0
@@ -182,15 +184,15 @@ timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
 timing__setup_vio__count__corner:min_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:min_ff_n40C_1v95,Infinity
 timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
-timing__unannotated_net__count__corner:min_ff_n40C_1v95,37
-timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
+timing__unannotated_net__count__corner:min_ff_n40C_1v95,74
+timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,1
 design__max_slew_violation__count__corner:max_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:max_tt_025C_1v80,0
 design__max_cap_violation__count__corner:max_tt_025C_1v80,0
 clock__skew__worst_hold__corner:max_tt_025C_1v80,0.0
 clock__skew__worst_setup__corner:max_tt_025C_1v80,0.0
-timing__hold__ws__corner:max_tt_025C_1v80,7.934230386161114
-timing__setup__ws__corner:max_tt_025C_1v80,11.35638903947831
+timing__hold__ws__corner:max_tt_025C_1v80,0.6856978512409907
+timing__setup__ws__corner:max_tt_025C_1v80,14.09233569725727
 timing__hold__tns__corner:max_tt_025C_1v80,0.0
 timing__setup__tns__corner:max_tt_025C_1v80,0.0
 timing__hold__wns__corner:max_tt_025C_1v80,0
@@ -201,15 +203,15 @@ timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
 timing__setup_vio__count__corner:max_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity
 timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
-timing__unannotated_net__count__corner:max_tt_025C_1v80,37
-timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
+timing__unannotated_net__count__corner:max_tt_025C_1v80,74
+timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,1
 design__max_slew_violation__count__corner:max_ss_100C_1v60,0
 design__max_fanout_violation__count__corner:max_ss_100C_1v60,0
 design__max_cap_violation__count__corner:max_ss_100C_1v60,0
 clock__skew__worst_hold__corner:max_ss_100C_1v60,0.0
 clock__skew__worst_setup__corner:max_ss_100C_1v60,0.0
-timing__hold__ws__corner:max_ss_100C_1v60,8.108038914206292
-timing__setup__ws__corner:max_ss_100C_1v60,10.986471598995426
+timing__hold__ws__corner:max_ss_100C_1v60,1.6259736239867688
+timing__setup__ws__corner:max_ss_100C_1v60,12.273434171932918
 timing__hold__tns__corner:max_ss_100C_1v60,0.0
 timing__setup__tns__corner:max_ss_100C_1v60,0.0
 timing__hold__wns__corner:max_ss_100C_1v60,0
@@ -220,15 +222,15 @@ timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
 timing__setup_vio__count__corner:max_ss_100C_1v60,0
 timing__setup_r2r__ws__corner:max_ss_100C_1v60,Infinity
 timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
-timing__unannotated_net__count__corner:max_ss_100C_1v60,37
-timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
+timing__unannotated_net__count__corner:max_ss_100C_1v60,74
+timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,1
 design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
 design__max_fanout_violation__count__corner:max_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.0
 clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.0
-timing__hold__ws__corner:max_ff_n40C_1v95,7.870254892780763
-timing__setup__ws__corner:max_ff_n40C_1v95,11.49101646360872
+timing__hold__ws__corner:max_ff_n40C_1v95,0.3602139799509259
+timing__setup__ws__corner:max_ff_n40C_1v95,14.693068511087631
 timing__hold__tns__corner:max_ff_n40C_1v95,0.0
 timing__setup__tns__corner:max_ff_n40C_1v95,0.0
 timing__hold__wns__corner:max_ff_n40C_1v95,0
@@ -239,19 +241,19 @@ timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:max_ff_n40C_1v95,Infinity
 timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0
-timing__unannotated_net__count__corner:max_ff_n40C_1v95,37
-timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0
-timing__unannotated_net__count,37
-timing__unannotated_net_filtered__count,0
+timing__unannotated_net__count__corner:max_ff_n40C_1v95,74
+timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,1
+timing__unannotated_net__count,74
+timing__unannotated_net_filtered__count,1
 design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.8
 design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8
-design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.00000222258
-design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.000002214
-design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,5.0838E-8
-design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.000002214
+design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.00000292441
+design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000246238
+design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,3.46096E-8
+design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000246238
 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
-ir__drop__avg,4.610000000000000251962960586861461909080617260769940912723541259765625E-8
-ir__drop__worst,0.0000022199999999999999207166319348250027587710064835846424102783203125
+ir__drop__avg,3.759999999999999919850151111101743683917675298289395868778228759765625E-8
+ir__drop__worst,0.0000029199999999999999949194286197329262222410761751234531402587890625
 magic__drc_error__count,0
 magic__illegal_overlap__count,0
 design__lvs_device_difference__count,0

projects/tt_um_wokwi_413923150973445121/stats/synthesis-stats.txt

@@ -14,40 +14,95 @@
 
    Chip area for module '\and_cell': 7.507200
 
+=== dff_cell ===
+
+   Number of wires:                  4
+   Number of wire bits:              4
+   Number of public wires:           4
+   Number of public wire bits:       4
+   Number of memories:               0
+   Number of memory bits:            0
+   Number of processes:              0
+   Number of cells:                  2
+     sky130_fd_sc_hd__dfxtp_2        1
+     sky130_fd_sc_hd__inv_2          1
+
+   Chip area for module '\dff_cell': 25.024000
+
+=== not_cell ===
+
+   Number of wires:                  2
+   Number of wire bits:              2
+   Number of public wires:           2
+   Number of public wire bits:       2
+   Number of memories:               0
+   Number of memory bits:            0
+   Number of processes:              0
+   Number of cells:                  1
+     sky130_fd_sc_hd__inv_2          1
+
+   Chip area for module '\not_cell': 3.753600
+
+=== or_cell ===
+
+   Number of wires:                  3
+   Number of wire bits:              3
+   Number of public wires:           3
+   Number of public wire bits:       3
+   Number of memories:               0
+   Number of memory bits:            0
+   Number of processes:              0
+   Number of cells:                  1
+     sky130_fd_sc_hd__or2_2          1
+
+   Chip area for module '\or_cell': 6.256000
+
 === tt_um_wokwi_413923150973445121 ===
 
-   Number of wires:                 10
-   Number of wire bits:             45
-   Number of public wires:          10
-   Number of public wire bits:      45
+   Number of wires:                 44
+   Number of wire bits:             79
+   Number of public wires:          44
+   Number of public wire bits:      79
    Number of memories:               0
    Number of memory bits:            0
    Number of processes:              0
-   Number of cells:                 26
-     and_cell                        2
-     sky130_fd_sc_hd__buf_2          5
-     sky130_fd_sc_hd__conb_1        19
+   Number of cells:                 57
+     and_cell                        9
+     dff_cell                        4
+     not_cell                        3
+     or_cell                        17
+     sky130_fd_sc_hd__buf_2          7
+     sky130_fd_sc_hd__conb_1        17
 
+   Area for cell type \dff_cell is unknown!
    Area for cell type \and_cell is unknown!
+   Area for cell type \not_cell is unknown!
+   Area for cell type \or_cell is unknown!
 
-   Chip area for module '\tt_um_wokwi_413923150973445121': 96.342400
+   Chip area for module '\tt_um_wokwi_413923150973445121': 98.844800
 
 === design hierarchy ===
 
    tt_um_wokwi_413923150973445121      1
-     and_cell                        2
+     and_cell                        9
+     dff_cell                        4
+     not_cell                        3
+     or_cell                        17
 
-   Number of wires:                 16
-   Number of wire bits:             51
-   Number of public wires:          16
-   Number of public wire bits:      51
+   Number of wires:                144
+   Number of wire bits:            179
+   Number of public wires:         144
+   Number of public wire bits:     179
    Number of memories:               0
    Number of memory bits:            0
    Number of processes:              0
-   Number of cells:                 26
-     sky130_fd_sc_hd__and2_2         2
-     sky130_fd_sc_hd__buf_2          5
-     sky130_fd_sc_hd__conb_1        19
+   Number of cells:                 61
+     sky130_fd_sc_hd__and2_2         9
+     sky130_fd_sc_hd__buf_2          7
+     sky130_fd_sc_hd__conb_1        17
+     sky130_fd_sc_hd__dfxtp_2        4
+     sky130_fd_sc_hd__inv_2          7
+     sky130_fd_sc_hd__or2_2         17
 
-   Chip area for top module '\tt_um_wokwi_413923150973445121': 111.356800
+   Chip area for top module '\tt_um_wokwi_413923150973445121': 384.118400