Skip to content

Commit

Permalink
feat: update project tt_um_senolgulgonul from senolgulgonul/tt09-seno…
Browse files Browse the repository at this point in the history 
…lgulgonul

Commit: d92f06d6ae123e8817d1124692f40e26944da9f1
Workflow: https://github.com/senolgulgonul/tt09-senolgulgonul/actions/runs/11723961689
  • Loading branch information
@TinyTapeoutBot @urish
TinyTapeoutBot authored and urish committed Nov 7, 2024
1 parent 7913cdd commit b9b7518
Show file tree
Hide file tree
Showing 7 changed files with 435 additions and 388 deletions.
4 changes: 2 additions & 2 deletions projects/tt_um_senolgulgonul/commit_id.json
View file
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
{
"app": "Tiny Tapeout tt09 a48b1c74",
"repo": "https://github.com/senolgulgonul/tt09-senolgulgonul",
"commit": "2bafa19bd627f72071b189c1c3173297d98a2501",
"workflow_url": "https://github.com/senolgulgonul/tt09-senolgulgonul/actions/runs/11710162896",
"commit": "d92f06d6ae123e8817d1124692f40e26944da9f1",
"workflow_url": "https://github.com/senolgulgonul/tt09-senolgulgonul/actions/runs/11723961689",
"sort_id": 1730725111692,
"openlane_version": "OpenLane2 2.1.9",
"pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"
Expand Down
10 changes: 5 additions & 5 deletions projects/tt_um_senolgulgonul/info.yaml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@ project:
title: "Senol Gulgonul tt09" # Project title
author: "Senol Gulgonul" # Your name
discord: "" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
description: "Display my name letters on 7-Seg at each button click" # One line description of what your project does
description: "Display the letters of SEnOLGULGONUL on 7-Seg using internal oscillator" # One line description of what your project does
language: "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
clock_hz: 0 # Clock frequency in Hz (or 0 if not applicable)

Expand All @@ -22,8 +22,8 @@ project:
# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
pinout:
# Inputs
ui[0]: ""
ui[1]: ""
ui[0]: "inv3_in"
ui[1]: "inv1_in"
ui[2]: ""
ui[3]: ""
ui[4]: ""
Expand All @@ -42,8 +42,8 @@ pinout:
uo[7]: "dp"

# Bidirectional pins
uio[0]: ""
uio[1]: ""
uio[0]: "inv3_out"
uio[1]: "inv2_out"
uio[2]: ""
uio[3]: ""
uio[4]: ""
Expand Down
164 changes: 82 additions & 82 deletions projects/tt_um_senolgulgonul/stats/metrics.csv
View file
Original file line number Diff line number Diff line change
@@ -1,23 +1,23 @@
Metric,Value
design__lint_error__count,0
design__lint_timing_construct__count,0
design__lint_warning__count,0
design__lint_warning__count,1
design__inferred_latch__count,0
design__instance__count,289
design__instance__area,942.154
design__instance__count,291
design__instance__area,965.926
design__instance_unmapped__count,0
synthesis__check_error__count,0
design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
design__max_fanout_violation__count__corner:nom_tt_025C_1v80,0
design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
power__internal__total,0.00005628330836771056
power__switching__total,0.000011626812010945287
power__leakage__total,1.9286874319845992E-9
power__total,0.00006791204941691831
clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.0012925494374000175
clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.0012925494374000175
timing__hold__ws__corner:nom_tt_025C_1v80,0.33075532138237423
timing__setup__ws__corner:nom_tt_025C_1v80,14.704005540457139
power__internal__total,0.00005841313031851314
power__switching__total,0.000012353103556961287
power__leakage__total,1.9285466557050768E-9
power__total,0.00007076816109474748
clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.00261807249956396
clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.00261807249956396
timing__hold__ws__corner:nom_tt_025C_1v80,0.3752770422858427
timing__setup__ws__corner:nom_tt_025C_1v80,11.47826755021178
timing__hold__tns__corner:nom_tt_025C_1v80,0.0
timing__setup__tns__corner:nom_tt_025C_1v80,0.0
timing__hold__wns__corner:nom_tt_025C_1v80,0
Expand All @@ -31,10 +31,10 @@ timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
design__max_slew_violation__count__corner:nom_ss_100C_1v60,0
design__max_fanout_violation__count__corner:nom_ss_100C_1v60,0
design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.0014997448152305728
clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.0014997448152305728
timing__hold__ws__corner:nom_ss_100C_1v60,0.9373745378557752
timing__setup__ws__corner:nom_ss_100C_1v60,13.705788003573586
clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.003981259878903531
clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.003981259878903531
timing__hold__ws__corner:nom_ss_100C_1v60,0.9998261390694265
timing__setup__ws__corner:nom_ss_100C_1v60,11.280718900515021
timing__hold__tns__corner:nom_ss_100C_1v60,0.0
timing__setup__tns__corner:nom_ss_100C_1v60,0.0
timing__hold__wns__corner:nom_ss_100C_1v60,0
Expand All @@ -48,10 +48,10 @@ timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,0
design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.0012136403336930827
clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.0012136403336930827
timing__hold__ws__corner:nom_ff_n40C_1v95,0.11182885489706622
timing__setup__ws__corner:nom_ff_n40C_1v95,15.066204710254542
clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.00186713150225725
clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.00186713150225725
timing__hold__ws__corner:nom_ff_n40C_1v95,0.14265178331243708
timing__setup__ws__corner:nom_ff_n40C_1v95,11.558058837159033
timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
timing__hold__wns__corner:nom_ff_n40C_1v95,0
Expand All @@ -65,10 +65,10 @@ timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
design__max_slew_violation__count,0
design__max_fanout_violation__count,0
design__max_cap_violation__count,0
clock__skew__worst_hold,0.002018052448935568
clock__skew__worst_setup,0.0010730583392239918
timing__hold__ws,0.10889101040179083
timing__setup__ws,13.69707941392213
clock__skew__worst_hold,0.004094724675229225
clock__skew__worst_setup,0.0016133483894382704
timing__hold__ws,0.13986789899945587
timing__setup__ws,11.275407593415
timing__hold__tns,0.0
timing__setup__tns,0.0
timing__hold__wns,0
Expand All @@ -86,12 +86,12 @@ flow__errors__count,0
design__io,45
design__die__area,17954.7
design__core__area,16493.3
design__instance__count__stdcell,289
design__instance__area__stdcell,942.154
design__instance__count__stdcell,291
design__instance__area__stdcell,965.926
design__instance__count__macros,0
design__instance__area__macros,0
design__instance__utilization,0.0571234
design__instance__utilization__stdcell,0.0571234
design__instance__utilization,0.0585647
design__instance__utilization__stdcell,0.0585647
design__power_grid_violation__count__net:VPWR,0
design__power_grid_violation__count__net:VGND,0
design__power_grid_violation__count,0
Expand All @@ -100,44 +100,44 @@ timing__drv__floating__pins,0
design__instance__displacement__total,0
design__instance__displacement__mean,0
design__instance__displacement__max,0
route__wirelength__estimated,973.064
route__wirelength__estimated,1116.14
design__violations,0
design__instance__count__setup_buffer,0
design__instance__count__hold_buffer,1
antenna__violating__nets,0
antenna__violating__pins,0
route__antenna_violation__count,0
route__net,82
route__net,84
route__net__special,2
route__drc_errors__iter:1,29
route__wirelength__iter:1,1073
route__drc_errors__iter:2,6
route__wirelength__iter:2,1047
route__drc_errors__iter:3,13
route__wirelength__iter:3,1028
route__drc_errors__iter:1,55
route__wirelength__iter:1,1304
route__drc_errors__iter:2,4
route__wirelength__iter:2,1233
route__drc_errors__iter:3,2
route__wirelength__iter:3,1233
route__drc_errors__iter:4,0
route__wirelength__iter:4,1030
route__wirelength__iter:4,1229
route__drc_errors,0
route__wirelength,1030
route__vias,393
route__vias__singlecut,393
route__wirelength,1229
route__vias,424
route__vias__singlecut,424
route__vias__multicut,0
design__disconnected_pin__count,17
design__disconnected_pin__count,15
design__critical_disconnected_pin__count,0
route__wirelength__max,83.27
timing__unannotated_net__count__corner:nom_tt_025C_1v80,34
route__wirelength__max,90.99
timing__unannotated_net__count__corner:nom_tt_025C_1v80,30
timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
timing__unannotated_net__count__corner:nom_ss_100C_1v60,34
timing__unannotated_net__count__corner:nom_ss_100C_1v60,30
timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0
timing__unannotated_net__count__corner:nom_ff_n40C_1v95,34
timing__unannotated_net__count__corner:nom_ff_n40C_1v95,30
timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
design__max_slew_violation__count__corner:min_tt_025C_1v80,0
design__max_fanout_violation__count__corner:min_tt_025C_1v80,0
design__max_cap_violation__count__corner:min_tt_025C_1v80,0
clock__skew__worst_hold__corner:min_tt_025C_1v80,0.001138422721647429
clock__skew__worst_setup__corner:min_tt_025C_1v80,0.001138422721647429
timing__hold__ws__corner:min_tt_025C_1v80,0.32609837975157424
timing__setup__ws__corner:min_tt_025C_1v80,14.70882657305562
clock__skew__worst_hold__corner:min_tt_025C_1v80,0.0022805924461089403
clock__skew__worst_setup__corner:min_tt_025C_1v80,0.0022805924461089403
timing__hold__ws__corner:min_tt_025C_1v80,0.3682081965769825
timing__setup__ws__corner:min_tt_025C_1v80,11.48447414118418
timing__hold__tns__corner:min_tt_025C_1v80,0.0
timing__setup__tns__corner:min_tt_025C_1v80,0.0
timing__hold__wns__corner:min_tt_025C_1v80,0
Expand All @@ -148,15 +148,15 @@ timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
timing__setup_vio__count__corner:min_tt_025C_1v80,0
timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
timing__unannotated_net__count__corner:min_tt_025C_1v80,34
timing__unannotated_net__count__corner:min_tt_025C_1v80,30
timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
design__max_slew_violation__count__corner:min_ss_100C_1v60,0
design__max_fanout_violation__count__corner:min_ss_100C_1v60,0
design__max_cap_violation__count__corner:min_ss_100C_1v60,0
clock__skew__worst_hold__corner:min_ss_100C_1v60,0.0013118395629984417
clock__skew__worst_setup__corner:min_ss_100C_1v60,0.0013118395629984417
timing__hold__ws__corner:min_ss_100C_1v60,0.9300691036136761
timing__setup__ws__corner:min_ss_100C_1v60,13.713386370169017
clock__skew__worst_hold__corner:min_ss_100C_1v60,0.0034955372918928514
clock__skew__worst_setup__corner:min_ss_100C_1v60,0.0034955372918928514
timing__hold__ws__corner:min_ss_100C_1v60,0.992381538367255
timing__setup__ws__corner:min_ss_100C_1v60,11.290653176420328
timing__hold__tns__corner:min_ss_100C_1v60,0.0
timing__setup__tns__corner:min_ss_100C_1v60,0.0
timing__hold__wns__corner:min_ss_100C_1v60,0
Expand All @@ -167,15 +167,15 @@ timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
timing__setup_vio__count__corner:min_ss_100C_1v60,0
timing__setup_r2r__ws__corner:min_ss_100C_1v60,Infinity
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
timing__unannotated_net__count__corner:min_ss_100C_1v60,34
timing__unannotated_net__count__corner:min_ss_100C_1v60,30
timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:min_ff_n40C_1v95,0
design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.0010730583392239918
clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.0010730583392239918
timing__hold__ws__corner:min_ff_n40C_1v95,0.10889101040179083
timing__setup__ws__corner:min_ff_n40C_1v95,15.069725449609807
clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.0016133483894382704
clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.0016133483894382704
timing__hold__ws__corner:min_ff_n40C_1v95,0.13986789899945587
timing__setup__ws__corner:min_ff_n40C_1v95,11.562719109459001
timing__hold__tns__corner:min_ff_n40C_1v95,0.0
timing__setup__tns__corner:min_ff_n40C_1v95,0.0
timing__hold__wns__corner:min_ff_n40C_1v95,0
Expand All @@ -186,15 +186,15 @@ timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
timing__setup_vio__count__corner:min_ff_n40C_1v95,0
timing__setup_r2r__ws__corner:min_ff_n40C_1v95,Infinity
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
timing__unannotated_net__count__corner:min_ff_n40C_1v95,34
timing__unannotated_net__count__corner:min_ff_n40C_1v95,30
timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
design__max_slew_violation__count__corner:max_tt_025C_1v80,0
design__max_fanout_violation__count__corner:max_tt_025C_1v80,0
design__max_cap_violation__count__corner:max_tt_025C_1v80,0
clock__skew__worst_hold__corner:max_tt_025C_1v80,0.0017431057091111231
clock__skew__worst_setup__corner:max_tt_025C_1v80,0.0017431057091111231
timing__hold__ws__corner:max_tt_025C_1v80,0.33556303130418236
timing__setup__ws__corner:max_tt_025C_1v80,14.698308763912067
clock__skew__worst_hold__corner:max_tt_025C_1v80,0.002701894340293803
clock__skew__worst_setup__corner:max_tt_025C_1v80,0.002701894340293803
timing__hold__ws__corner:max_tt_025C_1v80,0.38285281584208364
timing__setup__ws__corner:max_tt_025C_1v80,11.474650887584476
timing__hold__tns__corner:max_tt_025C_1v80,0.0
timing__setup__tns__corner:max_tt_025C_1v80,0.0
timing__hold__wns__corner:max_tt_025C_1v80,0
Expand All @@ -205,15 +205,15 @@ timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
timing__setup_vio__count__corner:max_tt_025C_1v80,0
timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
timing__unannotated_net__count__corner:max_tt_025C_1v80,34
timing__unannotated_net__count__corner:max_tt_025C_1v80,30
timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
design__max_slew_violation__count__corner:max_ss_100C_1v60,0
design__max_fanout_violation__count__corner:max_ss_100C_1v60,0
design__max_cap_violation__count__corner:max_ss_100C_1v60,0
clock__skew__worst_hold__corner:max_ss_100C_1v60,0.002018052448935568
clock__skew__worst_setup__corner:max_ss_100C_1v60,0.002018052448935568
timing__hold__ws__corner:max_ss_100C_1v60,0.945075711106194
timing__setup__ws__corner:max_ss_100C_1v60,13.69707941392213
clock__skew__worst_hold__corner:max_ss_100C_1v60,0.004094724675229225
clock__skew__worst_setup__corner:max_ss_100C_1v60,0.004094724675229225
timing__hold__ws__corner:max_ss_100C_1v60,1.0115796264743346
timing__setup__ws__corner:max_ss_100C_1v60,11.275407593415
timing__hold__tns__corner:max_ss_100C_1v60,0.0
timing__setup__tns__corner:max_ss_100C_1v60,0.0
timing__hold__wns__corner:max_ss_100C_1v60,0
Expand All @@ -224,15 +224,15 @@ timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
timing__setup_vio__count__corner:max_ss_100C_1v60,0
timing__setup_r2r__ws__corner:max_ss_100C_1v60,Infinity
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
timing__unannotated_net__count__corner:max_ss_100C_1v60,34
timing__unannotated_net__count__corner:max_ss_100C_1v60,30
timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:max_ff_n40C_1v95,0
design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.0016473350927408176
clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.0016473350927408176
timing__hold__ws__corner:max_ff_n40C_1v95,0.11517728763403584
timing__setup__ws__corner:max_ff_n40C_1v95,15.061735396320211
clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.0019437507709111346
clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.0019437507709111346
timing__hold__ws__corner:max_ff_n40C_1v95,0.1458264661411389
timing__setup__ws__corner:max_ff_n40C_1v95,11.555295714017198
timing__hold__tns__corner:max_ff_n40C_1v95,0.0
timing__setup__tns__corner:max_ff_n40C_1v95,0.0
timing__hold__wns__corner:max_ff_n40C_1v95,0
Expand All @@ -243,19 +243,19 @@ timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
timing__setup_vio__count__corner:max_ff_n40C_1v95,0
timing__setup_r2r__ws__corner:max_ff_n40C_1v95,Infinity
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0
timing__unannotated_net__count__corner:max_ff_n40C_1v95,34
timing__unannotated_net__count__corner:max_ff_n40C_1v95,30
timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0
timing__unannotated_net__count,34
timing__unannotated_net__count,30
timing__unannotated_net_filtered__count,0
design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79995
design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79996
design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8
design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000467214
design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000460914
design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000119085
design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000460914
design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000447712
design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000350783
design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000120046
design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000350783
ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
ir__drop__avg,0.00000119000000000000004144145963891343598106686840765178203582763671875
ir__drop__worst,0.00004669999999999999672206651979422531439922749996185302734375
ir__drop__avg,0.000001219999999999999965968520108938744073157067759893834590911865234375
ir__drop__worst,0.0000447999999999999979727154097997043891155044548213481903076171875
magic__drc_error__count,0
magic__illegal_overlap__count,0
design__lvs_device_difference__count,0
Expand Down
41 changes: 21 additions & 20 deletions projects/tt_um_senolgulgonul/stats/synthesis-stats.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2,34 +2,35 @@

=== tt_um_senolgulgonul ===

Number of wires: 41
Number of wire bits: 76
Number of wires: 40
Number of wire bits: 75
Number of public wires: 12
Number of public wire bits: 47
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 57
sky130_fd_sc_hd__a21o_2 1
sky130_fd_sc_hd__a21oi_2 2
sky130_fd_sc_hd__a31o_2 1
sky130_fd_sc_hd__and2_2 1
sky130_fd_sc_hd__and2b_2 1
sky130_fd_sc_hd__and3_2 2
sky130_fd_sc_hd__and4b_2 1
sky130_fd_sc_hd__buf_2 1
sky130_fd_sc_hd__conb_1 16
Number of cells: 56
sky130_fd_sc_hd__a21oi_2 3
sky130_fd_sc_hd__a22o_2 1
sky130_fd_sc_hd__a31o_2 2
sky130_fd_sc_hd__a32o_2 1
sky130_fd_sc_hd__and3_2 1
sky130_fd_sc_hd__and3b_2 1
sky130_fd_sc_hd__buf_2 2
sky130_fd_sc_hd__conb_1 14
sky130_fd_sc_hd__dfrtp_2 11
sky130_fd_sc_hd__inv_2 4
sky130_fd_sc_hd__mux2_1 2
sky130_fd_sc_hd__nor2_2 7
sky130_fd_sc_hd__nor3_2 1
sky130_fd_sc_hd__mux2_1 3
sky130_fd_sc_hd__nand2_2 2
sky130_fd_sc_hd__nand2b_2 2
sky130_fd_sc_hd__nand4_2 1
sky130_fd_sc_hd__nor2_2 1
sky130_fd_sc_hd__nor3_2 2
sky130_fd_sc_hd__o21a_2 1
sky130_fd_sc_hd__o21ba_2 1
sky130_fd_sc_hd__o22a_2 1
sky130_fd_sc_hd__o31ai_2 1
sky130_fd_sc_hd__o21ai_2 1
sky130_fd_sc_hd__o311a_2 1
sky130_fd_sc_hd__o31a_2 1
sky130_fd_sc_hd__or2_2 1
sky130_fd_sc_hd__xnor2_2 1

Chip area for module '\tt_um_senolgulgonul': 586.812800
Chip area for module '\tt_um_senolgulgonul': 596.822400

Binary file modified projects/tt_um_senolgulgonul/tt_um_senolgulgonul.gds
View file
Binary file not shown.
Loading

0 comments on commit b9b7518

Please sign in to comment.