feat: update project tt_um_rebeccargb_vga_timing_experiments from Reb…

…eccaRGB/vga-timing-experiments

Commit: 817b852ad0c1431e7837be62efc7a9ec47e3084a
Workflow: https://github.com/RebeccaRGB/vga-timing-experiments/actions/runs/11711729643

projects/tt_um_rebeccargb_vga_timing_experiments/commit_id.json

@@ -1,8 +1,8 @@
 {
-  "app": "Tiny Tapeout tt09 05f4c62d",
+  "app": "Tiny Tapeout tt09 a48b1c74",
   "repo": "https://github.com/RebeccaRGB/vga-timing-experiments",
-  "commit": "77be1e84765b2815d7d087f95a15859a4ab48d5b",
-  "workflow_url": "https://github.com/RebeccaRGB/vga-timing-experiments/actions/runs/11469834550",
+  "commit": "817b852ad0c1431e7837be62efc7a9ec47e3084a",
+  "workflow_url": "https://github.com/RebeccaRGB/vga-timing-experiments/actions/runs/11711729643",
   "sort_id": 1729722517344,
   "openlane_version": "OpenLane2 2.1.9",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"

projects/tt_um_rebeccargb_vga_timing_experiments/stats/metrics.csv

@@ -12,8 +12,8 @@ design__max_fanout_violation__count__corner:nom_tt_025C_1v80,2
 design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
 power__internal__total,0.0002801049849949777
 power__switching__total,0.00022335520770866424
-power__leakage__total,1.2298219331796645E-8
-power__total,0.0005034724599681795
+power__leakage__total,1.370134405931367E-8
+power__total,0.0005034738569520414
 clock__skew__worst_hold__corner:nom_tt_025C_1v80,4.66510088208332
 clock__skew__worst_setup__corner:nom_tt_025C_1v80,4.66510088208332
 timing__hold__ws__corner:nom_tt_025C_1v80,0.33909775946995285
@@ -92,8 +92,8 @@ design__instance__count__macros,0
 design__instance__area__macros,0
 design__instance__utilization,0.763465
 design__instance__utilization__stdcell,0.763465
-design__power_grid_violation__count__net:VGND,0
 design__power_grid_violation__count__net:VPWR,0
+design__power_grid_violation__count__net:VGND,0
 design__power_grid_violation__count,0
 timing__drv__floating__nets,0
 timing__drv__floating__pins,0
@@ -255,13 +255,13 @@ timing__unannotated_net__count,18
 timing__unannotated_net_filtered__count,0
 design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79994
 design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.79999
-design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000646541
-design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000731747
-design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000855667
-design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000731747
+design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000617279
+design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000561626
+design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000803148
+design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000561626
 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
-ir__drop__avg,0.000008559999999999999358533953053296272628358565270900726318359375
-ir__drop__worst,0.000064700000000000000566213742558829835616052150726318359375
+ir__drop__avg,0.0000084400000000000005074586584274953793283202685415744781494140625
+ir__drop__worst,0.000061699999999999995408013486741793940382194705307483673095703125
 magic__drc_error__count,0
 magic__illegal_overlap__count,0
 design__lvs_device_difference__count,0