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feat: update project tt_um_wokwi_413386991502909441 from parallellogi…
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…c-/TinyTapeoutLogic2024A

Commit: d6be687f74bebc59ffe3a60895f4014474a9cab5
Workflow: https://github.com/parallellogic-/TinyTapeoutLogic2024A/actions/runs/11763813925
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TinyTapeoutBot authored and urish committed Nov 10, 2024
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4 changes: 2 additions & 2 deletions projects/tt_um_wokwi_413386991502909441/commit_id.json
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
{
"app": "Tiny Tapeout tt09 a48b1c74",
"repo": "https://github.com/parallellogic-/TinyTapeoutLogic2024A",
"commit": "0fcb1fedaf6c05f196e4a815b11fc1bf3cf14554",
"workflow_url": "https://github.com/parallellogic-/TinyTapeoutLogic2024A/actions/runs/11763319531",
"commit": "d6be687f74bebc59ffe3a60895f4014474a9cab5",
"workflow_url": "https://github.com/parallellogic-/TinyTapeoutLogic2024A/actions/runs/11763813925",
"sort_id": 1730503332763,
"openlane_version": "OpenLane2 2.1.9",
"pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"
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4 changes: 2 additions & 2 deletions projects/tt_um_wokwi_413386991502909441/info.yaml
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Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
# Tiny Tapeout project information
project:
title: "Charlieplexing" # Project title
title: "SPI Logic Analyzer with Charlieplexed Display" # Project title
author: "ParallelLogic-" # Your name
discord: "ParallelLogic" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
description: "SPI LED Display Charlieplexer" # One line description of what your project does
description: "Displays contents of register map on charlieplexed display. Generates waveforms for PWM, UART, WS2812 in response to trigger." # One line description of what your project does
language: "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
clock_hz: 10000000 # Clock frequency in Hz (or 0 if not applicable)

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182 changes: 91 additions & 91 deletions projects/tt_um_wokwi_413386991502909441/stats/metrics.csv
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Original file line number Diff line number Diff line change
@@ -1,23 +1,23 @@
Metric,Value
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design__lint_timing_construct__count,0
design__lint_warning__count,11
design__lint_warning__count,0
design__inferred_latch__count,0
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power__total,0.0012863902375102043
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power__internal__total,0.0008643144392408431
power__switching__total,0.00046338161337189376
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power__total,0.0013277216348797083
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clock__skew__worst_setup__corner:nom_tt_025C_1v80,-0.0842415605561729
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timing__hold__wns__corner:nom_tt_025C_1v80,0
Expand All @@ -28,13 +28,13 @@ timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80,0
timing__setup_vio__count__corner:nom_tt_025C_1v80,0
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Expand All @@ -46,12 +46,12 @@ timing__setup_vio__count__corner:nom_ss_100C_1v60,0
timing__setup_r2r__ws__corner:nom_ss_100C_1v60,Infinity
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Expand All @@ -62,13 +62,13 @@ timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95,0
timing__setup_vio__count__corner:nom_ff_n40C_1v95,0
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Expand All @@ -86,12 +86,12 @@ flow__errors__count,0
design__io,45
design__die__area,75602.5
design__core__area,72564.6
design__instance__count__stdcell,3165
design__instance__area__stdcell,22758.1
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Expand All @@ -100,48 +100,48 @@ timing__drv__floating__pins,0
design__instance__displacement__total,0
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route__wirelength__estimated,100102
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route__drc_errors__iter:2,1347
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clock__skew__worst_hold__corner:min_tt_025C_1v80,-0.039329984826581496
clock__skew__worst_setup__corner:min_tt_025C_1v80,-0.039329984826581496
timing__hold__ws__corner:min_tt_025C_1v80,0.35704945566318674
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timing__setup__ws__corner:min_tt_025C_1v80,4.147547311877977
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timing__hold__wns__corner:min_tt_025C_1v80,0
Expand All @@ -154,13 +154,13 @@ timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
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Expand All @@ -174,12 +174,12 @@ timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
timing__unannotated_net__count__corner:min_ss_100C_1v60,27
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clock__skew__worst_hold__corner:min_ff_n40C_1v95,-0.05856237882609233
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Expand All @@ -193,12 +193,12 @@ timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
timing__unannotated_net__count__corner:min_ff_n40C_1v95,27
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clock__skew__worst_hold__corner:max_tt_025C_1v80,-0.09107298506450229
clock__skew__worst_setup__corner:max_tt_025C_1v80,-0.09107298506450229
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timing__hold__wns__corner:max_tt_025C_1v80,0
Expand All @@ -211,13 +211,13 @@ timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
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timing__hold__ws__corner:max_ss_100C_1v60,0.966967200347189
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Expand All @@ -231,12 +231,12 @@ timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
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clock__skew__worst_hold__corner:max_ff_n40C_1v95,-0.06965145324312252
clock__skew__worst_setup__corner:max_ff_n40C_1v95,-0.06965145324312252
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Expand All @@ -253,13 +253,13 @@ timing__unannotated_net__count,27
timing__unannotated_net_filtered__count,0
design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79994
design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8
design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000551489
design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000900303
design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000544209
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design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000691621
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ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
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ir__drop__worst,0.000064999999999999994305770190106130712592857889831066131591796875
magic__drc_error__count,0
magic__illegal_overlap__count,0
design__lvs_device_difference__count,0
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