feat: update project tt_um_wokwi_414120248222232577 from mng2/tt09-wokwi

Commit: 43f4031280837dd3aaa56504b57ff42a7e3e6bad
Workflow: https://github.com/mng2/tt09-wokwi/actions/runs/11764607283

projects/tt_um_wokwi_414120248222232577/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout tt09 a48b1c74",
   "repo": "https://github.com/mng2/tt09-wokwi",
-  "commit": "0079ed4eb7acbc0a6191d6566ae5aa55709855b6",
-  "workflow_url": "https://github.com/mng2/tt09-wokwi/actions/runs/11760730953",
+  "commit": "43f4031280837dd3aaa56504b57ff42a7e3e6bad",
+  "workflow_url": "https://github.com/mng2/tt09-wokwi/actions/runs/11764607283",
   "sort_id": 1731202479570,
   "openlane_version": "OpenLane2 2.1.9",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"

projects/tt_um_wokwi_414120248222232577/docs/info.md

@@ -1,13 +1,20 @@
 
-
 ## How it works
 
-Does stuff
+This design contains two NCOs, implemented with phase accumulators and sine lookup tables.
+The outputs of the NCOs are multiplied together by default.
+NCO B can be bypassed to a constant "one" or "half".
+There is also a boxcar filter for funsies.
+
+When operating at 50 MHz, it should be possible to tune NCO A from 24.8 MHz to 0.195 MHz.
+NCO B has one less bit in its increment control, so it can only go up to 12.3 MHz.
 
 ## How to test
 
-Testing is for the weak
+The output is intended for something simple like an R-2R DAC.
+Don't expect it to be pretty at high frequency.
 
 ## External hardware
 
-Add stuff
+* DAC
+* Oscilloscope 

projects/tt_um_wokwi_414120248222232577/info.yaml

@@ -1,28 +1,36 @@
-# Tiny Tapeout project information (Wokwi project)
+# Tiny Tapeout project information
 project:
-  wokwi_id:     414120248222232577       # Set this to the ID of your Wokwi project (the number from the project's URL)
-  title:        "Test"      # Project title
-  author:       "mng2"      # Your name
+  title:        "A Tale of Two NCOs"      # Project title
+  author:       "Mike Ng"      # Your name
   discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description:  "not a whole lot"      # One line description of what your project does
-  language:     "Wokwi" # other examples include SystemVerilog, Amaranth, VHDL, etc
-  clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
+  description:  "Two NCOs enter, one signal leaves"      # One line description of what your project does
+  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
+  clock_hz:     50000000       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
   tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
 
+  # Your top module name must start with "tt_um_". Make it unique by including your github username:
+  top_module:  "tt_um_wokwi_414120248222232577"
+
+  # List your project's source files here.
+  # Source files must be in ./src and you must list each source file separately, one per line.
+  # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
+  source_files:
+    - "sine_table.v"
+    - "project.v"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:
   # Inputs
-  ui[0]: "IN0"
-  ui[1]: "IN1"
-  ui[2]: "IN2"
-  ui[3]: "IN3"
-  ui[4]: "IN4"
-  ui[5]: "IN5"
-  ui[6]: "IN6"
-  ui[7]: "IN7"
+  ui[0]: "phase_incr_A[0]"
+  ui[1]: "phase_incr_A[1]"
+  ui[2]: "phase_incr_A[2]"
+  ui[3]: "phase_incr_A[3]"
+  ui[4]: "phase_incr_A[4]"
+  ui[5]: "phase_incr_A[5]"
+  ui[6]: "phase_incr_A[6]"
+  ui[7]: "filter_on"
 
   # Outputs
   uo[0]: "OUT0"
@@ -35,14 +43,14 @@ pinout:
   uo[7]: "OUT7"
 
   # Bidirectional pins
-  uio[0]: "BID0"
-  uio[1]: "BID1"
-  uio[2]: "BID2"
-  uio[3]: "BID3"
-  uio[4]: "BID4"
-  uio[5]: "BID5"
-  uio[6]: "BID6"
-  uio[7]: "BID7"
-
+  uio[0]: "phase_incr_B[0]"
+  uio[1]: "phase_incr_B[1]"
+  uio[2]: "phase_incr_B[2]"
+  uio[3]: "phase_incr_B[3]"
+  uio[4]: "phase_incr_B[4]"
+  uio[5]: "phase_incr_B[5]"
+  uio[6]: "low_amplitude_B"
+  uio[7]: "bypass_B"
+  
 # Do not change!
 yaml_version: 6