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feat: update project tt_um_senolgulgonul from senolgulgonul/tt09-seno…
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…lgulgonul

Commit: 21918c1c05d6a6f434cd4cb54d2dac90440da411
Workflow: https://github.com/senolgulgonul/tt09-senolgulgonul/actions/runs/11708849893
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@TinyTapeoutBot @urish
TinyTapeoutBot authored and urish committed Nov 6, 2024
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4 changes: 2 additions & 2 deletions projects/tt_um_senolgulgonul/commit_id.json
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
{
"app": "Tiny Tapeout tt09 a48b1c74",
"repo": "https://github.com/senolgulgonul/tt09-senolgulgonul",
"commit": "288ca74f0aea9d18a309147f2a8742d7b9beddf3",
"workflow_url": "https://github.com/senolgulgonul/tt09-senolgulgonul/actions/runs/11704449707",
"commit": "21918c1c05d6a6f434cd4cb54d2dac90440da411",
"workflow_url": "https://github.com/senolgulgonul/tt09-senolgulgonul/actions/runs/11708849893",
"sort_id": 1730725111692,
"openlane_version": "OpenLane2 2.1.9",
"pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"
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138 changes: 69 additions & 69 deletions projects/tt_um_senolgulgonul/stats/metrics.csv
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Original file line number Diff line number Diff line change
Expand Up @@ -3,21 +3,21 @@ design__lint_error__count,0
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design__instance__area,938.4
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power__internal__total,0.00005824807158205658
power__switching__total,0.00001219865407620091
power__leakage__total,1.8443998550665697E-9
power__total,0.00007044856465654448
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power__total,0.00006791204941691831
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clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.0012925494374000175
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Expand All @@ -31,10 +31,10 @@ timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
design__max_slew_violation__count__corner:nom_ss_100C_1v60,0
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Expand All @@ -48,10 +48,10 @@ timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0
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timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
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Expand All @@ -65,10 +65,10 @@ timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
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timing__setup__ws,13.69707941392213
timing__hold__tns,0.0
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timing__hold__wns,0
Expand All @@ -86,12 +86,12 @@ flow__errors__count,0
design__io,45
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design__instance__area__stdcell,938.4
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design__power_grid_violation__count__net:VPWR,0
design__power_grid_violation__count__net:VGND,0
design__power_grid_violation__count,0
Expand All @@ -100,31 +100,31 @@ timing__drv__floating__pins,0
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timing__unannotated_net__count__corner:nom_ss_100C_1v60,34
Expand All @@ -134,10 +134,10 @@ timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
design__max_slew_violation__count__corner:min_tt_025C_1v80,0
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clock__skew__worst_setup__corner:min_tt_025C_1v80,0.000486499743149896
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timing__setup__ws__corner:min_tt_025C_1v80,14.705980849318417
clock__skew__worst_hold__corner:min_tt_025C_1v80,0.001138422721647429
clock__skew__worst_setup__corner:min_tt_025C_1v80,0.001138422721647429
timing__hold__ws__corner:min_tt_025C_1v80,0.32609837975157424
timing__setup__ws__corner:min_tt_025C_1v80,14.70882657305562
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timing__hold__wns__corner:min_tt_025C_1v80,0
Expand All @@ -153,10 +153,10 @@ timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
design__max_slew_violation__count__corner:min_ss_100C_1v60,0
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clock__skew__worst_hold__corner:min_ss_100C_1v60,0.0007626677283359677
clock__skew__worst_setup__corner:min_ss_100C_1v60,0.0007626677283359677
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timing__setup__ws__corner:min_ss_100C_1v60,13.708269574148412
clock__skew__worst_hold__corner:min_ss_100C_1v60,0.0013118395629984417
clock__skew__worst_setup__corner:min_ss_100C_1v60,0.0013118395629984417
timing__hold__ws__corner:min_ss_100C_1v60,0.9300691036136761
timing__setup__ws__corner:min_ss_100C_1v60,13.713386370169017
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Expand All @@ -172,10 +172,10 @@ timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
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clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.00039143689397780595
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Expand All @@ -191,10 +191,10 @@ timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
design__max_slew_violation__count__corner:max_tt_025C_1v80,0
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clock__skew__worst_hold__corner:max_tt_025C_1v80,0.0010008105738532034
clock__skew__worst_setup__corner:max_tt_025C_1v80,0.0010008105738532034
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timing__setup__ws__corner:max_tt_025C_1v80,14.69342555882245
clock__skew__worst_hold__corner:max_tt_025C_1v80,0.0017431057091111231
clock__skew__worst_setup__corner:max_tt_025C_1v80,0.0017431057091111231
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Expand All @@ -210,10 +210,10 @@ timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
design__max_slew_violation__count__corner:max_ss_100C_1v60,0
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clock__skew__worst_hold__corner:max_ss_100C_1v60,0.0012515544510563162
clock__skew__worst_setup__corner:max_ss_100C_1v60,0.0012515544510563162
timing__hold__ws__corner:max_ss_100C_1v60,0.9452784378362241
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clock__skew__worst_hold__corner:max_ss_100C_1v60,0.002018052448935568
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timing__hold__ws__corner:max_ss_100C_1v60,0.945075711106194
timing__setup__ws__corner:max_ss_100C_1v60,13.69707941392213
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Expand All @@ -229,10 +229,10 @@ timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
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clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.0016473350927408176
clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.0016473350927408176
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Expand All @@ -249,13 +249,13 @@ timing__unannotated_net__count,34
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design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79995
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design__lvs_device_difference__count,0
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27 changes: 14 additions & 13 deletions projects/tt_um_senolgulgonul/stats/synthesis-stats.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -2,33 +2,34 @@

=== tt_um_senolgulgonul ===

Number of wires: 38
Number of wire bits: 73
Number of wires: 41
Number of wire bits: 76
Number of public wires: 12
Number of public wire bits: 47
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 54
sky130_fd_sc_hd__a211o_2 1
sky130_fd_sc_hd__a21boi_2 1
sky130_fd_sc_hd__a21o_2 2
Number of cells: 57
sky130_fd_sc_hd__a21o_2 1
sky130_fd_sc_hd__a21oi_2 2
sky130_fd_sc_hd__a31o_2 1
sky130_fd_sc_hd__and2_2 1
sky130_fd_sc_hd__and2b_2 1
sky130_fd_sc_hd__and3_2 2
sky130_fd_sc_hd__and4b_2 1
sky130_fd_sc_hd__buf_2 1
sky130_fd_sc_hd__conb_1 16
sky130_fd_sc_hd__dfrtp_2 11
sky130_fd_sc_hd__inv_2 4
sky130_fd_sc_hd__mux2_1 3
sky130_fd_sc_hd__nand2_2 2
sky130_fd_sc_hd__nand2b_2 1
sky130_fd_sc_hd__nor2_2 1
sky130_fd_sc_hd__o211a_2 1
sky130_fd_sc_hd__mux2_1 2
sky130_fd_sc_hd__nor2_2 7
sky130_fd_sc_hd__nor3_2 1
sky130_fd_sc_hd__o21a_2 1
sky130_fd_sc_hd__o21ba_2 1
sky130_fd_sc_hd__or3_2 2
sky130_fd_sc_hd__o22a_2 1
sky130_fd_sc_hd__o31ai_2 1
sky130_fd_sc_hd__or2_2 1
sky130_fd_sc_hd__xnor2_2 1

Chip area for module '\tt_um_senolgulgonul': 569.296000
Chip area for module '\tt_um_senolgulgonul': 586.812800

Binary file modified projects/tt_um_senolgulgonul/tt_um_senolgulgonul.gds
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