feat: update project tt_um_idann from arheidar/tt09-chip-tapeout-110

Commit: a2fd2f306936b9595db6abdaab07be0927413c81
Workflow: https://github.com/arheidar/tt09-chip-tapeout-110/actions/runs/11766611744

projects/tt_um_idann/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout tt09 a48b1c74",
   "repo": "https://github.com/arheidar/tt09-chip-tapeout-110",
-  "commit": "532f30dba9eb4c79a68414ce69b160af4681ac84",
-  "workflow_url": "https://github.com/arheidar/tt09-chip-tapeout-110/actions/runs/11741750976",
+  "commit": "a2fd2f306936b9595db6abdaab07be0927413c81",
+  "workflow_url": "https://github.com/arheidar/tt09-chip-tapeout-110/actions/runs/11766611744",
   "sort_id": 1731071060299,
   "openlane_version": "OpenLane2 2.1.9",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"

projects/tt_um_idann/docs/info.md

@@ -9,12 +9,13 @@ You can also include images in this folder and reference them in the markdown. E
 
 ## How it works
 
-will add soon
+The circuit takes in a 4-bit number, with each bit of the input representing an input neuron. It then completes the forward pass for the network, while also calculating the loss function (MSE).
 
 ## How to test
 
-will add soon
+To physically test the circuit, input a 4 bit-number into ui_in[3:0]. Use ui_in[7] to start the forward pass.  The final output calculation can be seen through the output pins {uio_out[1:0], uo_out[7:0]}. The current state can be seen through the output pins uio_out[7:5].
+To simulate the circuit, change the input value of ui_un on line 30 of "test.py". Using the .vcd file, analyze the output of the circuit using any waveform viewer.
 
 ## External hardware
 
-will add soon
+Use switches to connect to ui_in[3:0] (allowing for you to input a value). Connect a switch/button to ui_in[7] (allowing you to begin the forward pass).

projects/tt_um_idann/info.yaml

@@ -1,11 +1,11 @@
 # Tiny Tapeout project information
 project:
-  title:        "Simple identity mapping ANN"      # Project title
+  title:        "Forward Pass Network for Simple ANN"      # Project title
   author:       "Arian Heidari"      # Your name
   discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description:  "Simple ANN that takes in a 4bit value, and trains the output to mirror the input"      # One line description of what your project does
+  description:  "ANN that takes in a 4-bit value, and completes a forward pass"    # One line description of what your project does
   language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
-  clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
+  clock_hz:     50000000       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
   tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
@@ -20,29 +20,29 @@ project:
     - "tt_um_idann.v"
     - "hidden_neuron.v"
     - "output_neuron.v"
-    - "loss_calc.v"
+    - "state_mach.v"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:
   # Inputs
-  ui[0]: ""
-  ui[1]: ""
-  ui[2]: ""
-  ui[3]: ""
+  ui[0]: "Input bit [0]"
+  ui[1]: "Input bit [1]"
+  ui[2]: "Input bit [2]"
+  ui[3]: "Input bit [3]"
   ui[4]: ""
   ui[5]: ""
   ui[6]: ""
   ui[7]: ""
 
   # Outputs
-  uo[0]: "LFSR[0] output"
-  uo[1]: "LFSR[1] output"
-  uo[2]: "LFSR[2] output"
-  uo[3]: "LFSR[3] output"
-  uo[4]: "LFSR[4] output"
-  uo[5]: "LFSR[5] output"
-  uo[6]: "LFSR[6] output"
-  uo[7]: "LFSR[7] output"
+  uo[0]: "Output Calculation [0]"
+  uo[1]: "Output Calculation [1]"
+  uo[2]: "Output Calculation [2]"
+  uo[3]: "Output Calculation [3]"
+  uo[4]: "Output Calculation [4]"
+  uo[5]: "Output Calculation [5]"
+  uo[6]: "Output Calculation [6]"
+  uo[7]: "Output Calculation [7]"
 
   # Bidirectional pins
   uio[0]: ""

projects/tt_um_idann/stats/synthesis-stats.txt

@@ -2,17 +2,59 @@
 
 === tt_um_idann ===
 
-   Number of wires:                 10
-   Number of wire bits:             45
-   Number of public wires:           9
-   Number of public wire bits:      44
+   Number of wires:                448
+   Number of wire bits:            483
+   Number of public wires:          57
+   Number of public wire bits:      92
    Number of memories:               0
    Number of memory bits:            0
    Number of processes:              0
-   Number of cells:                 26
-     sky130_fd_sc_hd__buf_2          3
-     sky130_fd_sc_hd__conb_1        21
-     sky130_fd_sc_hd__dfrtp_2        2
+   Number of cells:                464
+     sky130_fd_sc_hd__a2111o_2       1
+     sky130_fd_sc_hd__a211o_2        3
+     sky130_fd_sc_hd__a21bo_2        5
+     sky130_fd_sc_hd__a21boi_2       5
+     sky130_fd_sc_hd__a21o_2        11
+     sky130_fd_sc_hd__a21oi_2       17
+     sky130_fd_sc_hd__a221o_2        1
+     sky130_fd_sc_hd__a22o_2         2
+     sky130_fd_sc_hd__a2bb2o_2       3
+     sky130_fd_sc_hd__a311oi_2       1
+     sky130_fd_sc_hd__a31o_2         3
+     sky130_fd_sc_hd__a32o_2         1
+     sky130_fd_sc_hd__and2_2        37
+     sky130_fd_sc_hd__and2b_2       17
+     sky130_fd_sc_hd__and3_2         9
+     sky130_fd_sc_hd__and3b_2        2
+     sky130_fd_sc_hd__buf_2         10
+     sky130_fd_sc_hd__conb_1        12
+     sky130_fd_sc_hd__dfrtp_2       11
+     sky130_fd_sc_hd__dfxtp_2       38
+     sky130_fd_sc_hd__dlxtn_1        1
+     sky130_fd_sc_hd__inv_2          9
+     sky130_fd_sc_hd__mux2_1         6
+     sky130_fd_sc_hd__nand2_2       33
+     sky130_fd_sc_hd__nand2b_2       5
+     sky130_fd_sc_hd__nand3b_2       2
+     sky130_fd_sc_hd__nor2_2        38
+     sky130_fd_sc_hd__nor3_2         1
+     sky130_fd_sc_hd__nor3b_2        1
+     sky130_fd_sc_hd__o211a_2       14
+     sky130_fd_sc_hd__o21a_2        27
+     sky130_fd_sc_hd__o21ai_2       12
+     sky130_fd_sc_hd__o21ba_2        7
+     sky130_fd_sc_hd__o21bai_2       2
+     sky130_fd_sc_hd__o221a_2        1
+     sky130_fd_sc_hd__o22a_2         2
+     sky130_fd_sc_hd__o2bb2a_2       1
+     sky130_fd_sc_hd__o311a_2        1
+     sky130_fd_sc_hd__o31a_2         2
+     sky130_fd_sc_hd__or2_2         27
+     sky130_fd_sc_hd__or3_2          2
+     sky130_fd_sc_hd__or3b_2         3
+     sky130_fd_sc_hd__or4_2          3
+     sky130_fd_sc_hd__xnor2_2       54
+     sky130_fd_sc_hd__xor2_2        21
 
-   Chip area for module '\tt_um_idann': 146.390400
+   Chip area for module '\tt_um_idann': 4972.268800