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feat: update project tt_um_project from stewedbeef/tt09-verilog-template
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Commit: b4ed758ea5c4646e4233ae2eedde885b13ac5b99
Workflow: https://github.com/stewedbeef/tt09-verilog-template/actions/runs/11765882493
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@TinyTapeoutBot @urish
TinyTapeoutBot authored and urish committed Nov 10, 2024
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4 changes: 2 additions & 2 deletions projects/tt_um_project/commit_id.json
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@@ -1,8 +1,8 @@
{
"app": "Tiny Tapeout tt09 a48b1c74",
"repo": "https://github.com/stewedbeef/tt09-verilog-template",
"commit": "414c412e1c5a7d0041500d250d8f399d207dd6af",
"workflow_url": "https://github.com/stewedbeef/tt09-verilog-template/actions/runs/11763288277",
"commit": "b4ed758ea5c4646e4233ae2eedde885b13ac5b99",
"workflow_url": "https://github.com/stewedbeef/tt09-verilog-template/actions/runs/11765882493",
"sort_id": 1731224450136,
"openlane_version": "OpenLane2 2.1.9",
"pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"
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6 changes: 3 additions & 3 deletions projects/tt_um_project/docs/info.md
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Expand Up @@ -9,12 +9,12 @@ You can also include images in this folder and reference them in the markdown. E

## How it works

Leaky integrate and fire neuron
This is a simple leaky integrate-and-fire neuron which performs the integration by addition and leaks by dividing by two every time step. The neuron has an enable pin which causes the neuron to enable and move forward in time roughly once every second when fed a clock of approximately 50 MHz.

## How to test

Put in input and expect output
The LED wired up to output seven should turn on and off approximately once every second, with a period of approximately two seconds, to allow synchronisation by the user. Each time the LED switches on or off a time step has occurred. The user should stimulate the neuron by "providing" an input current, which is achieved by switching the inputs manually to indicate to the neuron, in binary, how much current should flow in. With enough stimulus, the neuron will fire a spike, visible on LEDs zero to six, for one time period. The neuron has a timeout which prevents it from having a constant output from overstimulation.

## External hardware

LEDs and switches. All pins used
Wire switches to all input ports and LEDs to all output ports. Bidirectional ports are unused.
4 changes: 2 additions & 2 deletions projects/tt_um_project/info.yaml
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@@ -1,9 +1,9 @@
# Tiny Tapeout project information
project:
title: "title" # Project title
title: "Basic LIF Neuron" # Project title
author: "stewedbeef" # Your name
discord: "senorpineapplepizza" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
description: "description" # One line description of what your project does
description: "This is a basic LIF neuron" # One line description of what your project does
language: "SystemVerilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
clock_hz: 0 # Clock frequency in Hz (or 0 if not applicable)

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170 changes: 85 additions & 85 deletions projects/tt_um_project/stats/metrics.csv
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Original file line number Diff line number Diff line change
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Expand All @@ -28,13 +28,13 @@ timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80,0
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Expand All @@ -46,12 +46,12 @@ timing__setup_vio__count__corner:nom_ss_100C_1v60,0
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Expand All @@ -62,13 +62,13 @@ timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95,0
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Expand All @@ -86,12 +86,12 @@ flow__errors__count,0
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Expand All @@ -100,44 +100,44 @@ timing__drv__floating__pins,0
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Expand All @@ -150,13 +150,13 @@ timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity
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Expand All @@ -170,12 +170,12 @@ timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
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Expand All @@ -189,12 +189,12 @@ timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
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Expand All @@ -207,13 +207,13 @@ timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity
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Expand All @@ -227,12 +227,12 @@ timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
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Expand All @@ -247,15 +247,15 @@ timing__unannotated_net__count__corner:max_ff_n40C_1v95,28
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design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000602174
ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
ir__drop__avg,0.0000034400000000000000984433888573388315990086994133889675140380859375
ir__drop__worst,0.0000567000000000000026222947424603404442677856422960758209228515625
ir__drop__avg,0.000003559999999999999796551630737440063967369496822357177734375
ir__drop__worst,0.0000442999999999999993717698931749993107587215490639209747314453125
magic__drc_error__count,0
magic__illegal_overlap__count,0
design__lvs_device_difference__count,0
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