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Update project tt_um_rejunity_z80 (rejunity/z80-open-silicon) #213

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Jun 1, 2024
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Update project tt_um_rejunity_z80 (rejunity/z80-open-silicon) #213

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8 changes: 4 additions & 4 deletions projects/tt_um_rejunity_z80/commit_id.json
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@@ -1,9 +1,9 @@
{
"app": "Tiny Tapeout tt07 a6d2dae7",
"app": "Tiny Tapeout tt07 11b2d371",
"repo": "https://github.com/rejunity/z80-open-silicon",
"commit": "6adcf6188bf0cddb2c0845fd88982739f9f485d0",
"workflow_url": "https://github.com/rejunity/z80-open-silicon/actions/runs/8773945892",
"commit": "7f155e94b8a5fddfe23fb2f434564f9c2054590a",
"workflow_url": "https://github.com/rejunity/z80-open-silicon/actions/runs/9332415157",
"sort_id": 1713720108259,
"openlane_version": "OpenLane eaba5192c45aa333ab45216ce1773d75d539e9b3",
"openlane_version": "OpenLane 337ffbf4749b8bc6e8d8742ed9a595934142198b",
"pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"
}
101 changes: 98 additions & 3 deletions projects/tt_um_rejunity_z80/docs/info.md
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Expand Up @@ -9,12 +9,107 @@ You can also include images in this folder and reference them in the markdown. E

## How it works

This is a clone of a classic Zilog Z80 microprocessor
On April 15 of 2024 Zilog has [announced End-of-Life](https://www.mouser.com/PCN/Littelfuse_PCN_Z84C00.pdf) for Z80, one of the most famous 8-bit CPUs of all time. It is a time for open-source and hardware preservation community to step in with a Free and Open Source Silicon (FOSS) replacement for Zilog Z80.

The implementation is based around Guy Hutchison's [TV80](https://github.com/hutch31/tv80) Verilog core.

**The future work**
* Add thorough instruction (including 'illegal') execution tests [ZEXALL](https://mdfs.net/Software/Z80/Exerciser/) to testbench
* Compare different implementations: Verilog core [A-Z80](https://github.com/gdevic/A-Z80), Netlist based [Z80Explorer](https://github.com/gdevic/Z80Explorer)
* Create gate-level layouts that would resemble the original Z80 layout. Zilog designed Z80 by manually placing each transistor by hand.
* Tapeout QFN44 package
* Tapeout DIP40 package

**Z80 technical capabilities**
* nMOS original frequency 4MHz. CMOS frequency up to 20 MHz. This tapeout on 130 nm is expected to support frequency up to 50 MHz.
* 158 instructions including support for [Intel 8080A](https://en.wikipedia.org/wiki/Intel_8080) instruction set as a subset.
* Two sets of 6 general-purpose reigsters which may be used as either 8-bit or 16-bit register pairs.
* One maskable and one non-maskable interrupt.
* Instruction set derived from [Datapoint 2200](https://en.wikipedia.org/wiki/Datapoint_2200), [Intel 8008](https://en.wikipedia.org/wiki/Intel_8008) and [Intel 8080A](https://en.wikipedia.org/wiki/Intel_8080).

**Z80 registers**
* `AF`: 8-bit accumulator (A) and flag bits (F)
* `BC`: 16-bit data/address register or two 8-bit registers
* `DE`: 16-bit data/address register or two 8-bit registers
* `HL`: 16-bit accumulator/address register or two 8-bit registers
* `SP`: stack pointer, 16 bits
* `PC`: program counter, 16 bits
* `IX`: 16-bit index or base register for 8-bit immediate offsets
* `IY`: 16-bit index or base register for 8-bit immediate offsets
* `I`: interrupt vector base register, 8 bits
* `R`: DRAM refresh counter, 8 bits (msb does not count)
* `AF'`: alternate (or shadow) accumulator and flags (toggled in and out with `EX AF, AF'` )
* `BC'`, `DE'` and `HL'`: alternate (or shadow) registers (toggled in and out with `EXX`)

**Z80 Pinout**
```
,---------.__.---------.
<-- A11 |1 40| A10 -->
<-- A12 |2 39| A9 -->
<-- A13 |3 Z80 CPU 38| A8 -->
<-- A14 |4 37| A7 -->
<-- A15 |5 36| A6 -->
--> CLK |6 35| A5 -->
<-> D4 |7 34| A4 -->
<-> D3 |8 33| A3 -->
<-> D5 |9 32| A2 -->
<-> D6 |10 31| A1 -->
VCC |11 30| A0 -->
<-> D2 |12 29| GND
<-> D7 |13 28| /RFSH -->
<-> D0 |14 27| /M1 -->
<-> D1 |15 26| /RESET <--
--> /INT |16 25| /BUSRQ <--
--> /NMI |17 24| /WAIT <--
<-- /HALT |18 23| /BUSAK -->
<-- /MREQ |19 22| /WR -->
<-- /IORQ |20 21| /RD -->
`----------------------'
```

## How to test

Have to figure this out
Hold all `bidirectional` pins (**Data bus**) low to make CPU execute **NOP** instruction. **NOP** instruction opcode is 0.
Hold all `input` pins high to disable interrupts and signal that data bus is ready.

Every 4th cycle 8-bit value on `output` pins (**Address bus low 8-bit**) should monotonously increase.

```
Timing diagram, input pins

Z80CLK____ ____ ____ ____ ____ ____
__/ \____/ \____/ \____/ \____/ \____/ `____ ...
| | | | | |
| | | | | |

/RESET___________________________________________________________
__/
/WAIT ___________________________________________________________
__/
/INT ___________________________________________________________
__/
/NMI ___________________________________________________________
__/
/BUSRQ___________________________________________________________
__/

D7..D0 NOP NOP NOP NOP NOP
__ XXXXXXXXX ___#00___ ___#00___ ___#00___ ___#00___ ___#00___

Expected signals on output pins
/M1 _________ ____________________
\__________________/ \_________
/MREQ ___________________ ______________________________
\________/
/RD ___________________ ______________________________
\________/
A0..A7
__ XXXXXXXXX ___#00___ ___#00___ XXXXXXXXX XXXXXXXXX ___#01___

```

## External hardware

Bus de-multiplexor, external memory
Bus de-multiplexor, external memory, 8-bit computer such as [ZX Spectrum](https://en.wikipedia.org/wiki/ZX_Spectrum).

Alternatively the RP2040 on the TinyTapeout test PCB can be used to simulate RAM and I/O.
16 changes: 8 additions & 8 deletions projects/tt_um_rejunity_z80/info.yaml
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Expand Up @@ -35,14 +35,14 @@ pinout:
ui[7]: ""

# Outputs
uo[0]: "/M1 . A0 . A8"
uo[1]: "/MREQ . A1 . A9"
uo[2]: "/IORQ . A2 . A10"
uo[3]: "/RD . A3 . A11"
uo[4]: "/WR . A4 . A12"
uo[5]: "/RFSH . A5 . A13"
uo[6]: "/HALT . A6 . A14"
uo[7]: "/BUSAK . A7 . A15"
uo[0]: "/M1, A0, A8"
uo[1]: "/MREQ, A1, A9"
uo[2]: "/IORQ, A2, A10"
uo[3]: "/RD, A3, A11"
uo[4]: "/WR, A4, A12"
uo[5]: "/RFSH, A5, A13"
uo[6]: "/HALT, A6, A14"
uo[7]: "/BUSAK, A7, A15"

# Bidirectional pins
uio[0]: "D0"
Expand Down
2 changes: 1 addition & 1 deletion projects/tt_um_rejunity_z80/stats/metrics.csv
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design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
/work/src,tt_um_rejunity_z80,wokwi,flow completed,0h13m32s0ms,0h12m3s0ms,113488.2973618992,0.0756025088,56744.1486809496,57.85,58.8851,706.59,4122,0,0,0,0,0,0,0,25,19,0,-1,-1,211037,39693,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,146124773.0,0.0,73.87,68.05,56.95,36.02,-1,6411,7108,191,870,0,0,0,6653,185,19,147,347,1872,158,51,1446,385,380,27,2872,1037,93,1778,4290,10070,72564.5952,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,153.18,153.6,0.3,1,10,0.7,0,sky130_fd_sc_hd,AREA 0
/work/src,tt_um_rejunity_z80,wokwi,flow completed,0h9m15s0ms,0h7m59s0ms,110578.3410192864,0.0756025088,55289.1705096432,56.72,56.436699999999995,732.41,4023,0,0,0,0,0,0,0,22,16,0,-1,-1,195200,37358,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,140393175.0,0.0,69.96,58.42,53.42,34.9,-1,6413,7108,195,874,0,0,0,6648,184,19,145,346,1873,157,51,1445,383,377,27,3061,1037,69,1740,4180,10087,72564.5952,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,153.18,153.6,0.3,1,10,0.7,0,sky130_fd_sc_hd,AREA 0
138 changes: 68 additions & 70 deletions projects/tt_um_rejunity_z80/stats/synthesis-stats.txt
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=== tt_um_rejunity_z80 ===

Number of wires: 4106
Number of wire bits: 4141
Number of public wires: 369
Number of public wire bits: 404
Number of wires: 4007
Number of wire bits: 4042
Number of public wires: 366
Number of public wire bits: 401
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 4122
sky130_fd_sc_hd__a2111o_2 22
sky130_fd_sc_hd__a2111oi_2 1
sky130_fd_sc_hd__a211o_2 87
sky130_fd_sc_hd__a211oi_2 8
sky130_fd_sc_hd__a21bo_2 21
sky130_fd_sc_hd__a21boi_2 5
sky130_fd_sc_hd__a21o_2 113
sky130_fd_sc_hd__a21oi_2 86
sky130_fd_sc_hd__a221o_2 116
Number of cells: 4023
sky130_fd_sc_hd__a2111o_2 18
sky130_fd_sc_hd__a211o_2 68
sky130_fd_sc_hd__a211oi_2 5
sky130_fd_sc_hd__a21bo_2 37
sky130_fd_sc_hd__a21boi_2 7
sky130_fd_sc_hd__a21o_2 135
sky130_fd_sc_hd__a21oi_2 103
sky130_fd_sc_hd__a221o_2 102
sky130_fd_sc_hd__a221oi_2 2
sky130_fd_sc_hd__a22o_2 172
sky130_fd_sc_hd__a22oi_2 3
sky130_fd_sc_hd__a2bb2o_2 16
sky130_fd_sc_hd__a311o_2 19
sky130_fd_sc_hd__a31o_2 83
sky130_fd_sc_hd__a31oi_2 5
sky130_fd_sc_hd__a32o_2 31
sky130_fd_sc_hd__a41o_2 8
sky130_fd_sc_hd__and2_2 76
sky130_fd_sc_hd__and2b_2 29
sky130_fd_sc_hd__and3_2 103
sky130_fd_sc_hd__and3b_2 19
sky130_fd_sc_hd__and4_2 23
sky130_fd_sc_hd__and4b_2 16
sky130_fd_sc_hd__and4bb_2 10
sky130_fd_sc_hd__buf_1 503
sky130_fd_sc_hd__buf_2 9
sky130_fd_sc_hd__a22o_2 140
sky130_fd_sc_hd__a22oi_2 5
sky130_fd_sc_hd__a2bb2o_2 21
sky130_fd_sc_hd__a311o_2 17
sky130_fd_sc_hd__a31o_2 80
sky130_fd_sc_hd__a31oi_2 2
sky130_fd_sc_hd__a32o_2 39
sky130_fd_sc_hd__a41o_2 10
sky130_fd_sc_hd__and2_2 66
sky130_fd_sc_hd__and2b_2 43
sky130_fd_sc_hd__and3_2 92
sky130_fd_sc_hd__and3b_2 18
sky130_fd_sc_hd__and4_2 12
sky130_fd_sc_hd__and4b_2 10
sky130_fd_sc_hd__and4bb_2 7
sky130_fd_sc_hd__buf_1 521
sky130_fd_sc_hd__buf_2 10
sky130_fd_sc_hd__dfrtp_2 142
sky130_fd_sc_hd__dfstp_2 56
sky130_fd_sc_hd__dfxtp_2 172
sky130_fd_sc_hd__inv_2 112
sky130_fd_sc_hd__mux2_2 485
sky130_fd_sc_hd__dfxtp_2 170
sky130_fd_sc_hd__inv_2 102
sky130_fd_sc_hd__mux2_2 516
sky130_fd_sc_hd__mux4_2 16
sky130_fd_sc_hd__nand2_2 207
sky130_fd_sc_hd__nand2b_2 7
sky130_fd_sc_hd__nand3_2 8
sky130_fd_sc_hd__nand3b_2 6
sky130_fd_sc_hd__nand4_2 4
sky130_fd_sc_hd__nand4b_2 3
sky130_fd_sc_hd__nor2_2 295
sky130_fd_sc_hd__nor2b_2 5
sky130_fd_sc_hd__nor3_2 19
sky130_fd_sc_hd__nor3b_2 2
sky130_fd_sc_hd__nor4_2 3
sky130_fd_sc_hd__nor4b_2 1
sky130_fd_sc_hd__o2111a_2 12
sky130_fd_sc_hd__o211a_2 82
sky130_fd_sc_hd__o211ai_2 5
sky130_fd_sc_hd__o21a_2 104
sky130_fd_sc_hd__o21ai_2 79
sky130_fd_sc_hd__o21ba_2 18
sky130_fd_sc_hd__nand2_2 194
sky130_fd_sc_hd__nand2b_2 3
sky130_fd_sc_hd__nand3_2 9
sky130_fd_sc_hd__nand3b_2 2
sky130_fd_sc_hd__nand4_2 6
sky130_fd_sc_hd__nand4b_2 2
sky130_fd_sc_hd__nor2_2 232
sky130_fd_sc_hd__nor2b_2 8
sky130_fd_sc_hd__nor3_2 9
sky130_fd_sc_hd__nor3b_2 1
sky130_fd_sc_hd__nor4_2 5
sky130_fd_sc_hd__o2111a_2 4
sky130_fd_sc_hd__o211a_2 100
sky130_fd_sc_hd__o211ai_2 6
sky130_fd_sc_hd__o21a_2 77
sky130_fd_sc_hd__o21ai_2 66
sky130_fd_sc_hd__o21ba_2 20
sky130_fd_sc_hd__o21bai_2 10
sky130_fd_sc_hd__o221a_2 49
sky130_fd_sc_hd__o221a_2 61
sky130_fd_sc_hd__o221ai_2 4
sky130_fd_sc_hd__o22a_2 68
sky130_fd_sc_hd__o22a_2 69
sky130_fd_sc_hd__o22ai_2 2
sky130_fd_sc_hd__o2bb2a_2 35
sky130_fd_sc_hd__o311a_2 10
sky130_fd_sc_hd__o31a_2 32
sky130_fd_sc_hd__o31ai_2 3
sky130_fd_sc_hd__o32a_2 22
sky130_fd_sc_hd__o41a_2 7
sky130_fd_sc_hd__or2_2 166
sky130_fd_sc_hd__or2b_2 11
sky130_fd_sc_hd__or3_2 53
sky130_fd_sc_hd__or3b_2 25
sky130_fd_sc_hd__or4_2 60
sky130_fd_sc_hd__or4b_2 24
sky130_fd_sc_hd__or4bb_2 3
sky130_fd_sc_hd__xnor2_2 72
sky130_fd_sc_hd__xor2_2 37
sky130_fd_sc_hd__o2bb2a_2 18
sky130_fd_sc_hd__o311a_2 8
sky130_fd_sc_hd__o31a_2 27
sky130_fd_sc_hd__o31ai_2 4
sky130_fd_sc_hd__o32a_2 14
sky130_fd_sc_hd__o41a_2 6
sky130_fd_sc_hd__or2_2 159
sky130_fd_sc_hd__or2b_2 20
sky130_fd_sc_hd__or3_2 69
sky130_fd_sc_hd__or3b_2 26
sky130_fd_sc_hd__or4_2 78
sky130_fd_sc_hd__or4b_2 14
sky130_fd_sc_hd__or4bb_2 5
sky130_fd_sc_hd__xnor2_2 70
sky130_fd_sc_hd__xor2_2 43

Chip area for module '\tt_um_rejunity_z80': 40879.206400
Chip area for module '\tt_um_rejunity_z80': 40074.684800

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