Update project tt_um_maxluppe_NIST (maxluppe/tt07_maxluppe_NIST)

projects/tt_um_maxluppe_NIST/LICENSE

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projects/tt_um_maxluppe_NIST/commit_id.json

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+{
+  "app": "Tiny Tapeout tt07 11b2d371",
+  "repo": "https://github.com/maxluppe/tt07_maxluppe_NIST",
+  "commit": "3995571b501ae64a9cd4ae20d9cfe6c24268517b",
+  "workflow_url": "https://github.com/maxluppe/tt07_maxluppe_NIST/actions/runs/9331154875",
+  "sort_id": 1717255507639,
+  "openlane_version": "OpenLane 337ffbf4749b8bc6e8d8742ed9a595934142198b",
+  "pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"
+}

projects/tt_um_maxluppe_NIST/docs/info.md

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+<!---
+
+This file is used to generate your project datasheet. Please fill in the information below and delete any unused
+sections.
+
+You can also include images in this folder and reference them in the markdown. Each image must be less than
+512 kb in size, and the combined size of all images must be less than 1 MB.
+-->
+
+## How it works
+
+This project implements a LFSR where the D-type FFs (DFFs) are replaceded by configurable delay lines.
+
+![ALFSR diagram](alfsr.png)
+
+The configurable delay lines are implement using multiplexers and buffers. The buffers generate a delay line path and the multiplexer select differents paths according to its selection control signals. The selection control signals are generated by a conventional LFSR.
+
+It's expected that this circuit act as either as a convencional LFSR, or as an oscillator, or as a chaotic oscilator, according to the path generated by each delay line.
+
+To verify its functionality, four statistical tests from the NIST statistical suite are also implemented:
+1. The Frequency (Monobit) Test
+2. Frequency Test within a Block
+3. The Runs Test
+4. Tests for the Longest-Run-of-Ones in a Block
+
+They are choosen because they require at least 100 bits sequence to test.
+
+The implementations are based on the following works:
+- L. B. Carreira, P. Danielson, A. A. Rahimi, M. Luppe and S. Gupta, "Low-Latency Reconfigurable Entropy Digital True Random Number Generator With Bias Detection and Correction," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 5, pp. 1562-1575, May 2020, doi: 10.1109/TCSI.2019.2960694
+- V. B. Suresh, D. Antonioli and W. P. Burleson, "On-chip lightweight implementation of reduced NIST randomness test suite," 2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), Austin, TX, USA, 2013, pp. 93-98, doi: 10.1109/HST.2013.6581572.
+- F. Veljković, V. Rožić and I. Verbauwhede, "Low-cost implementations of on-the-fly tests for random number generators," 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, 2012, pp. 959-964, doi: 10.1109/DATE.2012.6176635.
+
+## How to use
+
+Explain how to use your project
+
+## External hardware
+
+List external hardware used in your project (e.g. PMOD, LED display, etc), if any

projects/tt_um_maxluppe_NIST/info.yaml

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+# Tiny Tapeout project information
+project:
+  title:        "Four NIST SP 800-22 tests implementation"      # Project title
+  author:       "Maximiliam Luppe"      # Your name
+  discord:      "maxluppe"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
+  description:  "Implementation of the first four NIST statistic tests"      # One line description of what your project does
+  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
+  clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
+
+  # How many tiles your design occupies? A single tile is about 167x108 uM.
+  tiles: "1x2"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
+
+  # Your top module name must start with "tt_um_". Make it unique by including your github username:
+  top_module:  "tt_um_maxluppe_NIST"
+
+  # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
+  source_files:        
+    - "tt_um_maxluppe_NIST.v"
+    - "NIST_SP_800_22.v"
+    - "NIST01.v"
+    - "NIST02.v"
+    - "NIST03.v"
+    - "NIST04.v"
+    - "NIST_commum.v"
+    - "alfsr.v"
+    - "alfsr_delay_line.v"
+    - "alfsr_modules.v"
+
+# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
+pinout:
+  # Inputs
+  ui[0]: "LFSR Configurator clock"
+  ui[1]: "ALFSR reset"
+  ui[2]: "NIST random bits input"
+  ui[3]: "Operation mode"
+  ui[4]: ""
+  ui[5]: ""
+  ui[6]: ""
+  ui[7]: ""
+
+  # Outputs
+  uo[0]: "NIST 01 test output"
+  uo[1]: "NIST 02 test output"
+  uo[2]: "NIST 03 test output"
+  uo[3]: "NIST 04 test output"
+  uo[4]: "NIST Global error output"
+  uo[5]: "LFSR Configurator output"
+  uo[6]: "ALFSR _digitalized_ output 3"
+  uo[7]: "ALFSR _analog_ output 3"
+
+  # Bidirectional pins
+  uio[0]: "ALFSR _analog_ output 0"
+  uio[1]: "ALFSR _analog_ output 1"
+  uio[2]: "ALFSR _analog_ output 2"
+  uio[3]: "ALFSR _analog_ output 3"
+  uio[4]: ""
+  uio[5]: ""
+  uio[6]: ""
+  uio[7]: ""
+
+# Do not change!
+yaml_version: 6

projects/tt_um_maxluppe_NIST/stats/metrics.csv

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+design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
+/work/src,tt_um_maxluppe_NIST,wokwi,flow completed,0h2m5s0ms,0h1m37s0ms,74503.34769842982,0.03634736,37251.67384921491,38.44,37.8881,564.84,1192,0,0,0,0,0,0,0,0,0,0,-1,-1,25777,8840,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,17550197.0,0.0,22.17,26.17,0.68,3.48,-1,1678,2329,647,1103,0,0,0,1375,56,1,43,37,119,155,33,287,152,163,17,1859,456,0,708,1354,4377,34255.3536,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,55.080,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0