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feat: update project tt_um_ender_clock from ender110/tt07-clock
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Commit: b97f18d7595e201d4dfb75756d9a1610bb36b896
Workflow: https://github.com/ender110/tt07-clock/actions/runs/9033817947
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TinyTapeoutBot authored and urish committed May 11, 2024
1 parent aa0aa7b commit ebc261b
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6 changes: 3 additions & 3 deletions projects/tt_um_ender_clock/commit_id.json
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
{
"app": "Tiny Tapeout tt07 65034f9c",
"app": "Tiny Tapeout tt07 68e6da5b",
"repo": "https://github.com/ender110/tt07-clock",
"commit": "cef4f7b2ff7cf6b6a57eb7299cfe711c44c28e80",
"workflow_url": "https://github.com/ender110/tt07-clock/actions/runs/8967681262",
"commit": "b97f18d7595e201d4dfb75756d9a1610bb36b896",
"workflow_url": "https://github.com/ender110/tt07-clock/actions/runs/9033817947",
"sort_id": 1714991718390,
"openlane_version": "OpenLane 337ffbf4749b8bc6e8d8742ed9a595934142198b",
"pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"
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4 changes: 4 additions & 0 deletions projects/tt_um_ender_clock/info.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,10 @@ project:
source_files:
- "project.v"
- "segment_show.v"
- "time_control.v"
- "segment_code.v"
- "day_of_month.v"
- "key.v"

# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
pinout:
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2 changes: 1 addition & 1 deletion projects/tt_um_ender_clock/stats/metrics.csv
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
/work/src,tt_um_ender_clock,wokwi,flow completed,0h1m20s0ms,0h1m2s0ms,44222.35490166374,0.01795472,22111.17745083187,24.72,26.786500000000004,518.46,338,0,0,0,0,0,0,0,0,0,0,-1,-1,7617,2625,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,4562013.0,0.0,18.16,11.5,1.31,0.24,-1,436,615,37,164,0,0,0,494,39,23,30,17,87,44,8,69,58,72,13,996,225,0,267,397,1885,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0
/work/src,tt_um_ender_clock,wokwi,flow completed,0h1m36s0ms,0h1m14s0ms,81538.44782876034,0.01795472,40769.22391438017,42.7,48.8469,529.51,580,0,0,0,0,0,0,0,0,0,0,-1,-1,12498,4481,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,6712067.0,0.0,29.37,20.88,2.33,0.39,-1,700,1025,106,401,0,0,0,758,39,45,62,27,157,52,22,58,133,147,15,749,225,0,330,732,2036,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0
101 changes: 51 additions & 50 deletions projects/tt_um_ender_clock/stats/synthesis-stats.txt
Original file line number Diff line number Diff line change
@@ -1,67 +1,68 @@

64. Printing statistics.
68. Printing statistics.

=== tt_um_ender_clock ===

Number of wires: 322
Number of wire bits: 357
Number of public wires: 65
Number of public wire bits: 100
Number of wires: 564
Number of wire bits: 599
Number of public wires: 140
Number of public wire bits: 175
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 338
sky130_fd_sc_hd__a2111o_2 1
sky130_fd_sc_hd__a2111oi_2 1
sky130_fd_sc_hd__a211o_2 5
sky130_fd_sc_hd__a211oi_2 1
sky130_fd_sc_hd__a21boi_2 2
sky130_fd_sc_hd__a21o_2 8
sky130_fd_sc_hd__a21oi_2 15
sky130_fd_sc_hd__a221oi_2 1
sky130_fd_sc_hd__a22o_2 8
Number of cells: 580
sky130_fd_sc_hd__a2111o_2 2
sky130_fd_sc_hd__a211o_2 3
sky130_fd_sc_hd__a21bo_2 1
sky130_fd_sc_hd__a21o_2 10
sky130_fd_sc_hd__a21oi_2 21
sky130_fd_sc_hd__a221o_2 1
sky130_fd_sc_hd__a22o_2 12
sky130_fd_sc_hd__a2bb2o_2 1
sky130_fd_sc_hd__a311o_2 1
sky130_fd_sc_hd__a31o_2 3
sky130_fd_sc_hd__a31oi_2 2
sky130_fd_sc_hd__a32o_2 3
sky130_fd_sc_hd__a32oi_2 1
sky130_fd_sc_hd__and2_2 15
sky130_fd_sc_hd__and2b_2 6
sky130_fd_sc_hd__and3_2 15
sky130_fd_sc_hd__and3b_2 4
sky130_fd_sc_hd__and4_2 6
sky130_fd_sc_hd__and4b_2 3
sky130_fd_sc_hd__and4bb_2 1
sky130_fd_sc_hd__buf_1 27
sky130_fd_sc_hd__a31o_2 6
sky130_fd_sc_hd__a32o_2 2
sky130_fd_sc_hd__a41o_2 2
sky130_fd_sc_hd__and2_2 21
sky130_fd_sc_hd__and2b_2 5
sky130_fd_sc_hd__and3_2 26
sky130_fd_sc_hd__and3b_2 7
sky130_fd_sc_hd__and4_2 5
sky130_fd_sc_hd__and4b_2 5
sky130_fd_sc_hd__and4bb_2 3
sky130_fd_sc_hd__buf_1 85
sky130_fd_sc_hd__buf_2 1
sky130_fd_sc_hd__conb_1 8
sky130_fd_sc_hd__dfrtp_2 50
sky130_fd_sc_hd__dfrtp_2 72
sky130_fd_sc_hd__dfstp_2 11
sky130_fd_sc_hd__dfxtp_2 2
sky130_fd_sc_hd__inv_2 9
sky130_fd_sc_hd__mux2_2 11
sky130_fd_sc_hd__nand2_2 13
sky130_fd_sc_hd__nand3_2 4
sky130_fd_sc_hd__nor2_2 36
sky130_fd_sc_hd__nor3_2 3
sky130_fd_sc_hd__nor3b_2 2
sky130_fd_sc_hd__o21a_2 8
sky130_fd_sc_hd__o21ai_2 5
sky130_fd_sc_hd__o21ba_2 1
sky130_fd_sc_hd__o21bai_2 3
sky130_fd_sc_hd__o22a_2 1
sky130_fd_sc_hd__dfxtp_2 47
sky130_fd_sc_hd__inv_2 18
sky130_fd_sc_hd__mux2_2 61
sky130_fd_sc_hd__nand2_2 17
sky130_fd_sc_hd__nand3_2 3
sky130_fd_sc_hd__nand4b_2 2
sky130_fd_sc_hd__nor2_2 44
sky130_fd_sc_hd__nor3_2 1
sky130_fd_sc_hd__nor3b_2 3
sky130_fd_sc_hd__nor4_2 1
sky130_fd_sc_hd__o2111ai_2 1
sky130_fd_sc_hd__o211a_2 2
sky130_fd_sc_hd__o211ai_2 1
sky130_fd_sc_hd__o21a_2 3
sky130_fd_sc_hd__o21ai_2 4
sky130_fd_sc_hd__o21bai_2 2
sky130_fd_sc_hd__o22ai_2 1
sky130_fd_sc_hd__o2bb2a_2 4
sky130_fd_sc_hd__o31a_2 1
sky130_fd_sc_hd__o32ai_2 1
sky130_fd_sc_hd__or2_2 8
sky130_fd_sc_hd__or2b_2 2
sky130_fd_sc_hd__o32a_2 1
sky130_fd_sc_hd__or2_2 9
sky130_fd_sc_hd__or2b_2 1
sky130_fd_sc_hd__or3_2 2
sky130_fd_sc_hd__or3b_2 3
sky130_fd_sc_hd__or4b_2 2
sky130_fd_sc_hd__or4bb_2 2
sky130_fd_sc_hd__xnor2_2 8
sky130_fd_sc_hd__xor2_2 7
sky130_fd_sc_hd__or4_2 8
sky130_fd_sc_hd__or4b_2 7
sky130_fd_sc_hd__or4bb_2 3
sky130_fd_sc_hd__xnor2_2 6
sky130_fd_sc_hd__xor2_2 14

Chip area for module '\tt_um_ender_clock': 3935.024000
Chip area for module '\tt_um_ender_clock': 6797.769600

Binary file modified projects/tt_um_ender_clock/tt_um_ender_clock.gds
Binary file not shown.
123 changes: 62 additions & 61 deletions projects/tt_um_ender_clock/tt_um_ender_clock.lef
Original file line number Diff line number Diff line change
Expand Up @@ -270,7 +270,7 @@ MACRO tt_um_ender_clock
PIN uio_out[0]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.933750 ;
ANTENNADIFFAREA 0.924000 ;
PORT
LAYER met4 ;
RECT 59.190 110.520 59.490 111.520 ;
Expand All @@ -297,7 +297,7 @@ MACRO tt_um_ender_clock
PIN uio_out[3]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.795200 ;
ANTENNADIFFAREA 0.445500 ;
PORT
LAYER met4 ;
RECT 48.150 110.520 48.450 111.520 ;
Expand Down Expand Up @@ -354,7 +354,8 @@ MACRO tt_um_ender_clock
PIN uo_out[1]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.891000 ;
ANTENNAGATEAREA 1.116000 ;
ANTENNADIFFAREA 0.795200 ;
PORT
LAYER met4 ;
RECT 84.950 110.520 85.250 111.520 ;
Expand All @@ -363,7 +364,7 @@ MACRO tt_um_ender_clock
PIN uo_out[2]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.891000 ;
ANTENNADIFFAREA 1.431000 ;
PORT
LAYER met4 ;
RECT 81.270 110.520 81.570 111.520 ;
Expand All @@ -372,7 +373,7 @@ MACRO tt_um_ender_clock
PIN uo_out[3]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.891000 ;
ANTENNADIFFAREA 2.001000 ;
PORT
LAYER met4 ;
RECT 77.590 110.520 77.890 111.520 ;
Expand All @@ -381,7 +382,7 @@ MACRO tt_um_ender_clock
PIN uo_out[4]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.891000 ;
ANTENNADIFFAREA 0.795200 ;
PORT
LAYER met4 ;
RECT 73.910 110.520 74.210 111.520 ;
Expand All @@ -390,7 +391,7 @@ MACRO tt_um_ender_clock
PIN uo_out[5]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.891000 ;
ANTENNADIFFAREA 0.445500 ;
PORT
LAYER met4 ;
RECT 70.230 110.520 70.530 111.520 ;
Expand All @@ -399,7 +400,7 @@ MACRO tt_um_ender_clock
PIN uo_out[6]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.891000 ;
ANTENNADIFFAREA 0.933750 ;
PORT
LAYER met4 ;
RECT 66.550 110.520 66.850 111.520 ;
Expand Down Expand Up @@ -439,62 +440,62 @@ MACRO tt_um_ender_clock
LAYER li1 ;
RECT 2.760 2.635 158.240 108.885 ;
LAYER met1 ;
RECT 2.760 2.480 159.040 109.040 ;
RECT 2.760 2.480 159.040 109.440 ;
LAYER met2 ;
RECT 4.230 2.535 159.010 110.005 ;
RECT 4.230 2.535 159.010 110.685 ;
LAYER met3 ;
RECT 3.950 2.555 159.030 109.985 ;
LAYER met4 ;
RECT 4.690 110.120 7.270 110.650 ;
RECT 8.370 110.120 10.950 110.650 ;
RECT 12.050 110.120 14.630 110.650 ;
RECT 15.730 110.120 18.310 110.650 ;
RECT 19.410 110.120 21.990 110.650 ;
RECT 23.090 110.120 25.670 110.650 ;
RECT 26.770 110.120 29.350 110.650 ;
RECT 30.450 110.120 33.030 110.650 ;
RECT 34.130 110.120 36.710 110.650 ;
RECT 37.810 110.120 40.390 110.650 ;
RECT 41.490 110.120 44.070 110.650 ;
RECT 45.170 110.120 47.750 110.650 ;
RECT 48.850 110.120 51.430 110.650 ;
RECT 52.530 110.120 55.110 110.650 ;
RECT 56.210 110.120 58.790 110.650 ;
RECT 59.890 110.120 62.470 110.650 ;
RECT 63.570 110.120 66.150 110.650 ;
RECT 67.250 110.120 69.830 110.650 ;
RECT 70.930 110.120 73.510 110.650 ;
RECT 74.610 110.120 77.190 110.650 ;
RECT 78.290 110.120 80.870 110.650 ;
RECT 81.970 110.120 84.550 110.650 ;
RECT 85.650 110.120 88.230 110.650 ;
RECT 89.330 110.120 91.910 110.650 ;
RECT 93.010 110.120 95.590 110.650 ;
RECT 96.690 110.120 99.270 110.650 ;
RECT 100.370 110.120 102.950 110.650 ;
RECT 104.050 110.120 106.630 110.650 ;
RECT 107.730 110.120 110.310 110.650 ;
RECT 111.410 110.120 113.990 110.650 ;
RECT 115.090 110.120 117.670 110.650 ;
RECT 118.770 110.120 121.350 110.650 ;
RECT 122.450 110.120 125.030 110.650 ;
RECT 126.130 110.120 128.710 110.650 ;
RECT 129.810 110.120 132.390 110.650 ;
RECT 133.490 110.120 136.070 110.650 ;
RECT 137.170 110.120 139.750 110.650 ;
RECT 140.850 110.120 143.430 110.650 ;
RECT 144.530 110.120 147.110 110.650 ;
RECT 148.210 110.120 150.790 110.650 ;
RECT 151.890 110.120 154.470 110.650 ;
RECT 3.950 2.555 159.030 110.665 ;
LAYER met4 ;
RECT 4.690 110.120 7.270 110.665 ;
RECT 8.370 110.120 10.950 110.665 ;
RECT 12.050 110.120 14.630 110.665 ;
RECT 15.730 110.120 18.310 110.665 ;
RECT 19.410 110.120 21.990 110.665 ;
RECT 23.090 110.120 25.670 110.665 ;
RECT 26.770 110.120 29.350 110.665 ;
RECT 30.450 110.120 33.030 110.665 ;
RECT 34.130 110.120 36.710 110.665 ;
RECT 37.810 110.120 40.390 110.665 ;
RECT 41.490 110.120 44.070 110.665 ;
RECT 45.170 110.120 47.750 110.665 ;
RECT 48.850 110.120 51.430 110.665 ;
RECT 52.530 110.120 55.110 110.665 ;
RECT 56.210 110.120 58.790 110.665 ;
RECT 59.890 110.120 62.470 110.665 ;
RECT 63.570 110.120 66.150 110.665 ;
RECT 67.250 110.120 69.830 110.665 ;
RECT 70.930 110.120 73.510 110.665 ;
RECT 74.610 110.120 77.190 110.665 ;
RECT 78.290 110.120 80.870 110.665 ;
RECT 81.970 110.120 84.550 110.665 ;
RECT 85.650 110.120 88.230 110.665 ;
RECT 89.330 110.120 91.910 110.665 ;
RECT 93.010 110.120 95.590 110.665 ;
RECT 96.690 110.120 99.270 110.665 ;
RECT 100.370 110.120 102.950 110.665 ;
RECT 104.050 110.120 106.630 110.665 ;
RECT 107.730 110.120 110.310 110.665 ;
RECT 111.410 110.120 113.990 110.665 ;
RECT 115.090 110.120 117.670 110.665 ;
RECT 118.770 110.120 121.350 110.665 ;
RECT 122.450 110.120 125.030 110.665 ;
RECT 126.130 110.120 128.710 110.665 ;
RECT 129.810 110.120 132.390 110.665 ;
RECT 133.490 110.120 136.070 110.665 ;
RECT 137.170 110.120 139.750 110.665 ;
RECT 140.850 110.120 143.430 110.665 ;
RECT 144.530 110.120 147.110 110.665 ;
RECT 148.210 110.120 150.790 110.665 ;
RECT 151.890 110.120 154.470 110.665 ;
RECT 3.975 109.440 155.185 110.120 ;
RECT 3.975 88.575 20.995 109.440 ;
RECT 23.395 88.575 40.430 109.440 ;
RECT 42.830 88.575 59.865 109.440 ;
RECT 62.265 88.575 79.300 109.440 ;
RECT 81.700 88.575 98.735 109.440 ;
RECT 101.135 88.575 118.170 109.440 ;
RECT 120.570 88.575 137.605 109.440 ;
RECT 140.005 88.575 155.185 109.440 ;
RECT 3.975 85.175 20.995 109.440 ;
RECT 23.395 85.175 40.430 109.440 ;
RECT 42.830 85.175 59.865 109.440 ;
RECT 62.265 85.175 79.300 109.440 ;
RECT 81.700 85.175 98.735 109.440 ;
RECT 101.135 85.175 118.170 109.440 ;
RECT 120.570 85.175 137.605 109.440 ;
RECT 140.005 85.175 155.185 109.440 ;
END
END tt_um_ender_clock
END LIBRARY
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