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feat: update project tt_um_ender_clock from ender110/tt07-clock
Commit: b97f18d7595e201d4dfb75756d9a1610bb36b896 Workflow: https://github.com/ender110/tt07-clock/actions/runs/9033817947
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design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY | ||
/work/src,tt_um_ender_clock,wokwi,flow completed,0h1m20s0ms,0h1m2s0ms,44222.35490166374,0.01795472,22111.17745083187,24.72,26.786500000000004,518.46,338,0,0,0,0,0,0,0,0,0,0,-1,-1,7617,2625,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,4562013.0,0.0,18.16,11.5,1.31,0.24,-1,436,615,37,164,0,0,0,494,39,23,30,17,87,44,8,69,58,72,13,996,225,0,267,397,1885,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0 | ||
/work/src,tt_um_ender_clock,wokwi,flow completed,0h1m36s0ms,0h1m14s0ms,81538.44782876034,0.01795472,40769.22391438017,42.7,48.8469,529.51,580,0,0,0,0,0,0,0,0,0,0,-1,-1,12498,4481,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,6712067.0,0.0,29.37,20.88,2.33,0.39,-1,700,1025,106,401,0,0,0,758,39,45,62,27,157,52,22,58,133,147,15,749,225,0,330,732,2036,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0 |
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64. Printing statistics. | ||
68. Printing statistics. | ||
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=== tt_um_ender_clock === | ||
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Number of wires: 322 | ||
Number of wire bits: 357 | ||
Number of public wires: 65 | ||
Number of public wire bits: 100 | ||
Number of wires: 564 | ||
Number of wire bits: 599 | ||
Number of public wires: 140 | ||
Number of public wire bits: 175 | ||
Number of memories: 0 | ||
Number of memory bits: 0 | ||
Number of processes: 0 | ||
Number of cells: 338 | ||
sky130_fd_sc_hd__a2111o_2 1 | ||
sky130_fd_sc_hd__a2111oi_2 1 | ||
sky130_fd_sc_hd__a211o_2 5 | ||
sky130_fd_sc_hd__a211oi_2 1 | ||
sky130_fd_sc_hd__a21boi_2 2 | ||
sky130_fd_sc_hd__a21o_2 8 | ||
sky130_fd_sc_hd__a21oi_2 15 | ||
sky130_fd_sc_hd__a221oi_2 1 | ||
sky130_fd_sc_hd__a22o_2 8 | ||
Number of cells: 580 | ||
sky130_fd_sc_hd__a2111o_2 2 | ||
sky130_fd_sc_hd__a211o_2 3 | ||
sky130_fd_sc_hd__a21bo_2 1 | ||
sky130_fd_sc_hd__a21o_2 10 | ||
sky130_fd_sc_hd__a21oi_2 21 | ||
sky130_fd_sc_hd__a221o_2 1 | ||
sky130_fd_sc_hd__a22o_2 12 | ||
sky130_fd_sc_hd__a2bb2o_2 1 | ||
sky130_fd_sc_hd__a311o_2 1 | ||
sky130_fd_sc_hd__a31o_2 3 | ||
sky130_fd_sc_hd__a31oi_2 2 | ||
sky130_fd_sc_hd__a32o_2 3 | ||
sky130_fd_sc_hd__a32oi_2 1 | ||
sky130_fd_sc_hd__and2_2 15 | ||
sky130_fd_sc_hd__and2b_2 6 | ||
sky130_fd_sc_hd__and3_2 15 | ||
sky130_fd_sc_hd__and3b_2 4 | ||
sky130_fd_sc_hd__and4_2 6 | ||
sky130_fd_sc_hd__and4b_2 3 | ||
sky130_fd_sc_hd__and4bb_2 1 | ||
sky130_fd_sc_hd__buf_1 27 | ||
sky130_fd_sc_hd__a31o_2 6 | ||
sky130_fd_sc_hd__a32o_2 2 | ||
sky130_fd_sc_hd__a41o_2 2 | ||
sky130_fd_sc_hd__and2_2 21 | ||
sky130_fd_sc_hd__and2b_2 5 | ||
sky130_fd_sc_hd__and3_2 26 | ||
sky130_fd_sc_hd__and3b_2 7 | ||
sky130_fd_sc_hd__and4_2 5 | ||
sky130_fd_sc_hd__and4b_2 5 | ||
sky130_fd_sc_hd__and4bb_2 3 | ||
sky130_fd_sc_hd__buf_1 85 | ||
sky130_fd_sc_hd__buf_2 1 | ||
sky130_fd_sc_hd__conb_1 8 | ||
sky130_fd_sc_hd__dfrtp_2 50 | ||
sky130_fd_sc_hd__dfrtp_2 72 | ||
sky130_fd_sc_hd__dfstp_2 11 | ||
sky130_fd_sc_hd__dfxtp_2 2 | ||
sky130_fd_sc_hd__inv_2 9 | ||
sky130_fd_sc_hd__mux2_2 11 | ||
sky130_fd_sc_hd__nand2_2 13 | ||
sky130_fd_sc_hd__nand3_2 4 | ||
sky130_fd_sc_hd__nor2_2 36 | ||
sky130_fd_sc_hd__nor3_2 3 | ||
sky130_fd_sc_hd__nor3b_2 2 | ||
sky130_fd_sc_hd__o21a_2 8 | ||
sky130_fd_sc_hd__o21ai_2 5 | ||
sky130_fd_sc_hd__o21ba_2 1 | ||
sky130_fd_sc_hd__o21bai_2 3 | ||
sky130_fd_sc_hd__o22a_2 1 | ||
sky130_fd_sc_hd__dfxtp_2 47 | ||
sky130_fd_sc_hd__inv_2 18 | ||
sky130_fd_sc_hd__mux2_2 61 | ||
sky130_fd_sc_hd__nand2_2 17 | ||
sky130_fd_sc_hd__nand3_2 3 | ||
sky130_fd_sc_hd__nand4b_2 2 | ||
sky130_fd_sc_hd__nor2_2 44 | ||
sky130_fd_sc_hd__nor3_2 1 | ||
sky130_fd_sc_hd__nor3b_2 3 | ||
sky130_fd_sc_hd__nor4_2 1 | ||
sky130_fd_sc_hd__o2111ai_2 1 | ||
sky130_fd_sc_hd__o211a_2 2 | ||
sky130_fd_sc_hd__o211ai_2 1 | ||
sky130_fd_sc_hd__o21a_2 3 | ||
sky130_fd_sc_hd__o21ai_2 4 | ||
sky130_fd_sc_hd__o21bai_2 2 | ||
sky130_fd_sc_hd__o22ai_2 1 | ||
sky130_fd_sc_hd__o2bb2a_2 4 | ||
sky130_fd_sc_hd__o31a_2 1 | ||
sky130_fd_sc_hd__o32ai_2 1 | ||
sky130_fd_sc_hd__or2_2 8 | ||
sky130_fd_sc_hd__or2b_2 2 | ||
sky130_fd_sc_hd__o32a_2 1 | ||
sky130_fd_sc_hd__or2_2 9 | ||
sky130_fd_sc_hd__or2b_2 1 | ||
sky130_fd_sc_hd__or3_2 2 | ||
sky130_fd_sc_hd__or3b_2 3 | ||
sky130_fd_sc_hd__or4b_2 2 | ||
sky130_fd_sc_hd__or4bb_2 2 | ||
sky130_fd_sc_hd__xnor2_2 8 | ||
sky130_fd_sc_hd__xor2_2 7 | ||
sky130_fd_sc_hd__or4_2 8 | ||
sky130_fd_sc_hd__or4b_2 7 | ||
sky130_fd_sc_hd__or4bb_2 3 | ||
sky130_fd_sc_hd__xnor2_2 6 | ||
sky130_fd_sc_hd__xor2_2 14 | ||
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Chip area for module '\tt_um_ender_clock': 3935.024000 | ||
Chip area for module '\tt_um_ender_clock': 6797.769600 | ||
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